ADG431 Ver la hoja de datos (PDF) - Analog Devices
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ADG431 Datasheet PDF : 8 Pages
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ADG431/ADG432/ADG433
120
VDD = +15V
VS
VG
VD
VS
VG
VD
VSS = –15V
VL = +5V
100
T
R
P+ P-CHANNEL P+
T
R
N+ N-CHANNEL N+
T
R
E
E
E
N
N
N
C
H
N–
C
H
P–
C
H
80
BURIED OXIDE LAYER
SUBSTRATE (BACKGATE)
60
Figure 1. Trench Isolation
40
100
1k
10k
100k
1M
10M
FREQUENCY – Hz
TPC 7. Off Isolation vs. Frequency
110
VDD = +15V
VSS = –15V
100
VL = +5V
90
80
70
60
100
1k
10k
100k
1M
10M
FREQUENCY – Hz
TPC 8. Crosstalk vs. Frequency
TRENCH ISOLATION
In the ADG431A, ADG432A and ADG433A, an insulating
oxide layer (trench) is placed between the NMOS and PMOS
transistors of each CMOS switch. Parasitic junctions, which
occur between the transistors in junction isolated switches, are
eliminated, the result being a completely latch-up proof switch.
In junction isolation, the N and P wells of the PMOS and NMOS
transistors from a diode that is reverse-biased under normal
operation. However, during overvoltage conditions, this diode
becomes forward biased. A silicon-controlled rectifier (SCR)
type circuit is formed by the two transistors causing a significant
amplification of the current which, in turn, leads to latch up.
With trench isolation, this diode is removed, the result being a
latch-up proof switch.
APPLICATION
Figure 2 illustrates a precise, fast sample-and-hold circuit.
An AD845 is used as the input buffer while the output opera-
tional amplifier is an AD711. During the track mode, SW1 is
closed and the output VOUT follows the input signal VIN. In
the hold mode, SW1 is opened and the signal is held by the
hold capacitor CH.
Due to switch and capacitor leakage, the voltage on the hold
capacitor will decrease with time. The ADG431/ADG432/
ADG433 minimizes this droop due to its low leakage specifica-
tions. The droop rate is further minimized by the use of a
polystyrene hold capacitor. The droop rate for the circuit
shown is typically 30 µV/µs.
A second switch SW2, which operates in parallel with SW1, is
included in this circuit to reduce pedestal error. Since both
switches will be at the same potential, they will have a differen-
tial effect on the op amp AD711 which will minimize charge
injection effects. Pedestal error is also reduced by the compensa-
tion network RC and CC. This compensation network also reduces
the hold time glitch while optimizing the acquisition time. Using
the illustrated op amps and component values, the pedestal error
has a maximum value of 5 mV over the ± 10 V input range. Both
the acquisition and settling times are 850 ns.
+15V
VIN
AD845
–15V
+15V +5V
2200pF
SW2
S
D
SW1
S
D
ADG431
ADG432
ADG433
+15V
RC
CC
1000pF
75⍀
CH
2200pF
AD711
–15V
VOUT
–15V
Figure 2. Fast, Accurate Sample-and-Hold
–6–
REV. C
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