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ADL5542 Datasheet PDF : 12 Pages
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ADL5542
BASIC CONNECTIONS
The basic connections for operating the ADL5542 are shown in
Figure 13. Recommended components are listed in Table 5. The
input and output should be ac-coupled with appropriately sized
capacitors (device characterization was performed with 33 pF
capacitors). A 5 V dc bias is supplied to the amplifier via VPOS
(Pin 5) and through a biasing inductor connected to RFOUT
(Pin 8). The bias voltage should be decoupled using a 1 μF
capacitor, a 1.2 nF capacitor, and two 68 pF capacitors.
RFIN
VCC
C1
33pF
C3
1µF
C6
C5
1µF
1.2nF
ADL5542
1 RFIN RFOUT 8
C4
68pF
L1
47nH
C2
33pF
2 GND GND 7
GND
3 GND GND 6
4 CB
VPOS 5
VCC
C7
68pF
RFOUT
Figure 13. Basic Connections
For operation between 50 MHz and 500 MHz, a larger biasing
choke and ac coupling capacitors are necessary (see Table 5).
Figure 14 shows a plot of the input return loss, the output
return loss, and the gain with these components. At 100 MHz,
the ADL5542 achieves an OIP3 of 38 dBm (POUT = 0 dBm per
tone). The noise figure performance for operation from 50 MHz
to 500 MHz is shown in Figure 15. When operating below
50 MHz, the ADL5542 exhibits gain peaking, and the input
and output match degrade significantly.
21.0
10
20.5
0
S21
20.0
–10
19.5
–20
S11
19.0
–30
S22
18.5
–40
18.0
–50
50 100 150 200 250 300 350 400 450 500
FREQUENCY (MHz)
Figure 14. Input Return Loss (S11), Output Return Loss (S22), and
Gain (S21) vs. Frequency
4.0
3.5
3.0
2.5
2.0
1.5
50
100 150 200 250 300 350 400 450 500
FREQUENCY (MHz)
Figure 15. Noise Figure vs. Frequency
SOLDERING INFORMATION AND RECOMMENDED
PCB LAND PATTERN
Figure 16 shows the recommended land pattern for the ADL5542.
To minimize thermal impedance, the exposed paddle on the
package underside should be soldered down to a ground plane
along with Pin 2, Pin 3, Pin 6, and Pin 7. If multiple ground
layers exist, they should be stitched together using vias (a
minimum of five vias is recommended). For more information
on land pattern design and layout, refer to Application Note
AN-772, A Design and Manufacturing Guide for the Lead Frame
Chip Scale Package (LFCSP).
2.03mm
PIN 1
PIN 8
0.5mm
1.85mm
1.78mm
PIN 4
PIN 5
0.71mm
1.53mm
Figure 16. Recommended Land Pattern
Table 5. Recommended Components for Basic Connections
Frequency
C1
C2
C3 L1
50 MHz to 500 MHz
0.1 μF 0.1 μF 1 μF 470 nH (Coilcraft 0603LS-471NXJL_ or equivalent)
500 MHz to 6000 MHz 33 pF 33 pF 1 μF 47 nH (Coilcraft 0603CS-47NXJL_ or equivalent)
C4
68 pF
68 pF
C5
1.2 nF
1.2 nF
C6 C7
1 μF 68 pF
1 μF 68 pF
Rev. A | Page 10 of 12
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