ADM6308 Ver la hoja de datos (PDF) - Unspecified

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ADM6308

Eight-port 10/100M Ethernet Switch Controller

Unspecified 

Olive plus Specification

4

Pin Descriptions

Pin Name Pin # Type

Descriptions

EEPROM Interface

EEDO

51 I EEDO: Data Output of serial EEPROM. Internally pull up (50K Ohm). Inputs configuration

information to ADM6308.

EEDI

50 BI EEDI: Data Input of serial EEPROM. Internally pull down (50K Ohm). ADM6308 outputs

4ma data to EEPROM

EESK

48 BI EESK: Clock input of serial EEPROM. Internally pull up. ADM6308 outputs clock signal to

4ma EEPROM

EECS

49 BI Chip Select of serial EEPROM. Internally pull down. EECK/s:50ns, h:0ns

4ma

Reduced MII Interface

TXE0

TXE1

TXE2

TXE3

TXE4

TXE5

TXE6

TXE7

TXD0[1:0]

TXD1[1:0]

TXD2[1:0]

TXD3[1:0]

TXD4[1:0]

TXD5[1:0]

TXD6[1:0]

TXD7[1:0]

72, 86

95, 2

12, 20

28, 35

O Transmit Enable. TXE0~7 shows that ADM6308 is presenting the recovered and decoded

8ma data on the TXD0~7[1:0].

TXE0~7 indicates that the MAC is presenting di-bits on TXD0~7[1:0] on the Reduced MII

for transmission. TXE0~7 shall be asserted synchronously with the first nibble of the

preamble and shall remain asserted while all di-bits to be transmitted are presented to the

Reduced MII. TXE0~7 shall be negative prior to the first REFCLK rising edge following

the final di-bit of a frame. TXE0~7 shall transition synchronously with REFCLK.

74, 73

88, 87,

97, 96

4,3

14, 13

22, 21

30, 29

37, 36

O Transmit Data. These bundle signals are output from ADM6308 to Reduced MII connecting

4ma device. These signals are transited synchronously with the rising edge of TXE0~7. When

TXE0~7 is being asserted, for each period of TXE0~7, ADM6308 drives the recovered and

encoded data into TXD0~7[1:0] for transmission. While TXE0~7 is de-asserted, the

TXD0~7[1:0] will have no effect upon the Reduced MII connecting device.

TXD0~7[1:0] shall transition synchronously with REFCLK. When TXE0~7 is being

asserted, TXD0~7[1:0] is accepted for transmission by the PHY. TXD0~7[1:0] shall be “00”

to indicate idle when TXE0~7 is de-asserted. Values of TXD0~7[1:0] other than “00” when

TXE0~7 is de-asserted are reserved for out-of-band signaling (to be defined). Values other

than “00” on TXD0~7[1:0] while TXE0~7 is de-asserted shall be ignored by the PHY.

TXC0

TXD0[3:2]

78

77, 76

BI Transmit Clock for port0 MII mode.

4ma

O Transmit Data for port0 MII mode.

4ma

ADMtek Incorporated

00/04/25

1F, No 9, Industrial E. 9th Road, SBIP, Hsin-Chu

Version : 1.10

Tel : (03)578-8879 Fax : (03)578-8871

ADMtek Incorporated Confidential

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