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ADM6926

26 port 10/100 Mbps Ethernet Switch Controller

Unspecified 

ADMtek Inc.

V1.0

Table of Contents

Chapter 1 Product Overview ........................................................................................ 1-1

1.1 Overview.......................................................................................................... 1-1

1.2 Features ............................................................................................................ 1-1

1.3 Block Diagram ................................................................................................. 1-2

1.4 Abbreviations................................................................................................... 1-3

1.5 Conventions ..................................................................................................... 1-4

1.5.1 Data Lengths............................................................................................ 1-4

1.5.2 Register Type Descriptions ...................................................................... 1-4

1.5.3 Pin Type Descriptions.............................................................................. 1-4

Chapter 2 Interface Description ................................................................................... 2-1

2.1 Pin Diagram – ADM6926 (SS-SMII Interface)..................................................... 2-1

2.2 Pin Description................................................................................................. 2-2

2.2.1 SS-SMII Networking Interface, 60 pins ................................................... 2-2

2.2.2 MII/RMII Interface, 28pins...................................................................... 2-3

2.2.3 Power/Ground.......................................................................................... 2-5

2.2.4 Miscellaneous pins, 16 pins ..................................................................... 2-5

Chapter 3 Function Description ................................................................................... 3-1

3.1.1 Basic Operation ....................................................................................... 3-1

3.1.2 Address Learning ..................................................................................... 3-1

3.1.3 Address Aging .......................................................................................... 3-2

3.1.4 Address Recognition and Packet Forwarding ......................................... 3-3

3.1.5 Trunking Port Forwarding ...................................................................... 3-4

3.1.6 Illegal Frames.......................................................................................... 3-4

3.1.7 Back off Algorithm ................................................................................... 3-4

3.1.8 Buffers and Queues .................................................................................. 3-4

3.1.9 Half Duplex Flow Control ....................................................................... 3-5

3.1.10 Full Duplex Flow Control........................................................................ 3-5

3.1.11 Inter-Packet Gap (IPG) ........................................................................... 3-5

3.1.13 Priority Control ....................................................................................... 3-6

3.1.14 Alert LED Display.................................................................................... 3-7

3.1.15 Broadcast Storm Filter ............................................................................ 3-7

3.1.16 Collision LED Display............................................................................. 3-7

3.1.17 Bandwidth Control................................................................................... 3-8

3.1.18 Smart Discard .......................................................................................... 3-8

3.1.19 Security Support....................................................................................... 3-8

3.1.20 Smart Counter Support ............................................................................ 3-8

3.1.21 Length 1536 Mode ................................................................................... 3-8

3.1.22 PHY Management (MDC/MDIO Interface)............................................. 3-8

3.1.23 Forward Special Packets to the CPU Port .............................................. 3-9

3.1.24 Special TAG ........................................................................................... 3-10

3.1.25 Port 24 and Port 25 Interface (Only SS-SMII package support)........... 3-12

3.1.26 Hardware, EEPROM and SMI Interface for Configuration.................. 3-13

3.2 EEPROM Register Format ............................................................................ 3-17

3.2.1 Signature (Index: 0h) ............................................................................. 3-20

3.2.2 Global Configuration Register (Index: 1h)............................................ 3-20

ADM6926

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