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ADM6996F

6 port 10/100 Mb/s Single Chip Ethernet Switch Controller

Infineon Technologies 

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V1.03

4.3.20 Port8 PVID bit 11~4 & VLAN group shift bits Configuration Register.. 4-1

4.3.21 Reserved Register, offset: 0x2dh.............................................................. 4-2

4.3.22 Reserved Register, offset: 0x2eh .............................................................. 4-2

4.3.23 PHY Restart, offset: 0x2fh........................................................................ 4-2

4.3.24 Miscellaneous Configuration Register, offset: 0x30h.............................. 4-2

4.3.25 Bandwidth Control Register0~3, offset: 0x31h........................................ 4-3

4.3.26 Bandwidth Control Register 4~5, offset: 0x32h....................................... 4-3

4.3.27 Bandwidth Control Enable Register, offset: 0x33h .................................. 4-4

4.4 EEPROM Access ............................................................................................. 4-4

4.5 Serial Register Map.......................................................................................... 4-6

4.6 Serial Register Description .............................................................................. 4-7

4.6.1 Chip Identifier Register, offset: 0x00h..................................................... 4-7

4.6.2 Port Status 0 Register, offset: 0x01h ....................................................... 4-7

4.6.3 Port Status 1 Register, offset: 0x02h ....................................................... 4-9

4.6.4 Cable Broken Status Register, offset: 0x03h............................................ 4-9

4.6.5 Over Flow Flag 0 Register, offset: 0x3ah.............................................. 4-10

4.6.6 Over Flow Flag 0: Register 0x3bh ........................................................ 4-10

4.6.7 Over Flow Flag 2 Register, offset: 0x3ch.............................................. 4-11

4.7 Serial Interface Timing .................................................................................... 4-1

4.8 PHY Register Description................................................................................ 4-2

4.8.1 Control Register, offset: 0x00 .................................................................. 4-2

4.8.2 Status Register, offset: 0x01..................................................................... 4-4

4.8.3 PHY Identifier Register, offset: 0x02 ....................................................... 4-5

4.8.4 PHY Identifier Register, offset: 0x03 ....................................................... 4-5

4.8.5 Auto Negotiation Advertisement Register, offset : 0x04 .......................... 4-6

4.8.6 Auto Negotiation Link Partner Ability Register, offset: 0x05.................. 4-7

4.8.7 Auto Negotiation Expansion Register, offset: 0x06 ................................. 4-7

4.8.8 Next Page Transmit Register, offset: 0x07 ............................................. 4-8

4.8.9 Link Partner Next Page Register, offset: 0x08 ........................................ 4-8

Chapter 5 Electrical Specification................................................................................ 5-1

5.1 TX/FX Interface............................................................................................... 5-1

5.1.1 TP Interface ............................................................................................. 5-1

5.1.2 FX Interface ............................................................................................. 5-1

5.2 DC Characteristics ........................................................................................... 5-2

5.2.1 Absolute Maximum Rating....................................................................... 5-2

5.2.2 Recommended Operating Conditions ...................................................... 5-2

5.2.3 DC Electrical Characteristics for 3.3V Operation .................................. 5-2

5.3 AC Characteristics ........................................................................................... 5-3

5.3.1 Power On Reset........................................................................................ 5-3

5.3.2 EEPROM Interface Timing...................................................................... 5-3

5.3.3 10Base-TX MII Input Timing ................................................................... 5-4

5.3.4 10Base-TX MII Output Timing ................................................................ 5-4

5.3.5 100Base-TX MII Input Timing ................................................................. 5-5

5.3.6 100Base-TX MII Output Timing .............................................................. 5-5

5.3.7 SMI Timing............................................................................................... 5-6

5.3.8 GPSI(7-wire) Input Timing ...................................................................... 5-6

ADM6996F

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