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EVAL-ADN2806EB
(Rev.:Rev0)

622 Mbps Clock and Data Recovery IC

Analog Devices 

ADN2806

Transmission Lines

Minimizing reflections in the ADN2806 requires use of 50 Ω

transmission lines for all pins with high frequency input and

output signals, including PIN, NIN, CLKOUTP, CLKOUTN,

DATAOUTP, and DATAOUTN (also REFCLKP and REFCLKN,

if a high frequency reference clock is used, such as 155 MHz). It

is also necessary for the PIN/NIN input traces to be matched in

length and for the CLKOUTP/CLKOUTN and

DATAOUTP/DATAOUTN output traces to be matched in

length to avoid skew between the differential traces.

The high speed inputs, PIN and NIN, are internally terminated

with 50 Ω to an internal reference voltage (see Figure 20).

A 0.1 μF is recommended between VREF, Pin 3, and GND to

provide an ac ground for the inputs.

As with any high speed, mixed-signal design, take care to keep

all high speed digital traces away from sensitive analog nodes.

ADN2806

LIM

50Ω CIN PIN

50Ω CIN NIN

50Ω 50Ω

0.1µF

VREF

3kΩ

2.5V

Figure 20. ADN2806 AC-Coupled Input Configuration

Soldering Guidelines for Lead Frame Chip Scale Package

The lands on the 32-lead LFCSP are rectangular. The printed

circuit board (PCB) pad for these should be 0.1 mm longer than

the package land length and 0.05 mm wider than the package

land width. The land should be centered on the pad. This

ensures that the solder joint size is maximized. The bottom of

the chip scale package has a central exposed pad. The pad on

the PCB should be at least as large as this exposed pad. The user

must connect the exposed pad to VEE using plugged vias so

that solder does not leak through the vias during reflow. This

ensures a solid connection from the exposed pad to VEE.

Choosing AC Coupling Capacitors

AC coupling capacitors at the input (PIN, NIN) and output

(DATAOUTP, DATAOUTN) of the ADN2806 can be optimized

for the application. When choosing the capacitors, the time

constant formed with the two 50 Ω resistors in the signal path

must be considered. When a large number of consecutive

identical digits (CIDs) are applied, the capacitor voltage can

droop due to baseline wander (see Figure 21), causing pattern-

dependent jitter (PDJ).

The user must determine how much droop is tolerable and

choose an ac coupling capacitor based on that amount of droop.

The amount of PDJ can then be approximated based on the

capacitor selection. The actual capacitor value selection can

require some trade-offs between droop and PDJ.

For example, assuming that 2% droop can be tolerated, the

maximum differential droop is 4%. Normalizing to V p-p:

Droop = ΔV = 0.04 V = 0.5 V p-p (1 − e−t/τ); therefore, τ = 12t

where:

τ is the RC time constant (C is the ac coupling capacitor, R =

100 Ω seen by C).

t is the total discharge time, which is equal to nT, where n is the

number of CIDs, and T is the bit period.

The capacitor value can then be calculated by combining the

equations for τ and t:

C = 12 nT/R

Once the capacitor value is selected, the PDJ can be

approximated as

PDJpspp = 0.5 tr(1 − e(−nT/RC))/0.6

where:

PDJpspp is the amount of pattern-dependent jitter allowed

(<0.01 UI p-p typical).

tr is the rise time, which is equal to 0.22/BW,

where BW ~ 0.7 (bit rate).

Note that this expression for tr is accurate only for the inputs.

The output rise time for the ADN2806 is ~100 ps regardless of

the data rate.

Rev. 0 | Page 18 of 20

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