EVAL-ADN2806EB(Rev0) Ver la hoja de datos (PDF) - Analog Devices
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EVAL-ADN2806EB Datasheet PDF : 20 Pages
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ADN2806
SPECIFICATIONS
TA = TMIN to TMAX, VCC = VMIN to VMAX, VEE = 0 V, CF = 0.47 μF, SLICEP = SLICEN = VEE, input data pattern: PRBS 223 − 1,
unless otherwise noted.
Table 1.
Parameter
DATA INPUTS—DC CHARACTERISTICS
Input Voltage Range
Peak-to-Peak Differential Input
Input Common-Mode Level
DATA INPUTS—AC CHARACTERISTICS
Data Rate
S11
Output Clock Range
Input Resistance
Input Capacitance
LOSS-OF-LOCK (LOL) DETECT
VCO Frequency Error for LOL Assert
VCO Frequency Error for LOL Deassert
LOL Response Time
ACQUISITION TIME
Lock to Data Mode
Optional Lock to REFCLK Mode
DATA RATE READBACK ACCURACY
Fine Readback
POWER SUPPLY VOLTAGE
POWER SUPPLY CURRENT
OPERATING TEMPERATURE RANGE
Conditions
@ PIN or NIN, dc-coupled
PIN − NIN
DC-coupled
@ 622 MHz
Absence of input data
Differential
With respect to nominal
With respect to nominal
OC-12
OC-12
In addition to REFCLK accuracy
OC-12
Locked to 622.08 Mbps
Min
Typ
Max
1.8
2.8
0.2
2.0
2.3
2.5
2.8
622
−15
622 ± 5%
100
0.65
1000
250
200
2.0
20.0
100
3.0
3.3
3.6
109
–40
+85
Unit
V
V
V
Mbps
dB
MHz
Ω
pF
ppm
ppm
μs
ms
ms
ppm
V
mA
°C
JITTER SPECIFICATIONS
TA = TMIN to TMAX, VCC = VMIN to VMAX, VEE = 0 V, CF = 0.47 μF, SLICEP = SLICEN = VEE, input data pattern: PRBS 223 − 1,
unless otherwise noted.
Table 2.
Parameter
PHASE-LOCKED LOOP CHARACTERISTICS
Jitter Transfer Bandwidth
Jitter Peaking
Jitter Generation
Jitter Tolerance
Conditions
Min
OC-12
OC-12
OC-12, 12 kHz to 5 MHz
OC-12, 223 − 1 PRBS
30 Hz1
100
300 Hz1
44
25 kHz
2.5
250 kHz1
1.0
Typ
75
0
0.001
0.011
Max
130
0.03
0.003
0.026
Unit
kHz
dB
UI rms
UI p-p
UI p-p
UI p-p
UI p-p
UI p-p
1 Jitter tolerance of the ADN2806 at these jitter frequencies is better than what the test equipment is able to measure.
Rev. 0 | Page 3 of 20
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