ADNB-3062 Ver la hoja de datos (PDF) - HP => Agilent Technologies
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ADNB-3062 Datasheet PDF : 38 Pages
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AC Electrical Specifications
Electrical Characteristics over recommended operating conditions. Typical values at 25 °C, VDD3=3.3V, fclk=24MHz.
Parameter
Symbol Minimum Typical Maximum Units Notes
VDD to RESET
tOP
250
µs From VDD = 3.0V to RESET sampled
Data delay after
RESET
tPU-RESET
35
ms From RESET falling edge to valid motion data at 2000
fps and shutter bound 8290.
Input delay after reset TIN-RST
500
µs From RESET falling edge to inputs active (NPD,
MOSI, NCS, SCLK)
Power Down
tPD
2.1
ms From NPD falling edge to initiate the power down
cycle at 500fps (tpd = 1 frame period + 100ms )
Wake from NPD
tPUPD
75
ms From NPD rising edge to valid motion data at 2000
fps and shutter bound 8290. Max assumes surface
change while NPD is low.
Data delay after NPD tCOMPUTE
3.1
ms From NPD rising edge to all registers contain data
from new images at 2000fps (see Figure 10) .
RESET pulse width tPW-RESET 10
µs
MISO rise time
tr-MISO
MISO fall time
tf-MISO
MISO delay after SCLK tDLY-MISO
40
200
40
200
120
ns CL = 50pF
ns CL = 50pF
ns From SCLK falling edge to MISO data valid, no load
conditions
MISO hold time
MOSI hold time
MOSI setup time
SPI time between
write commands
thold-MISO
thold-MOSI
tsetup-MOSI
tSWW
250
200
120
50
ns Data held until next falling SCLK edge
ns Amount of time data is valid after SCLK rising edge
ns From data valid to SCLK rising edge
µs From rising SCLK for last bit of the first data byte, to
rising SCLK for last bit of the second data byte.
SPI time between
tSWR
50
write and read
commands
µs From rising SCLK for last bit of the first data byte, to
rising SCLK for last bit of the second address byte.
SPI time between read tSRW
250
and subsequent
tSRR
commands
ns From rising SCLK for last bit of the first data byte, to
falling SCLK for first bit of the second address byte.
SPI read address-data tSRAD
50
delay
µs From rising SCLK for last bit of the address byte, to
falling SCLK for first bit of data being read. All
registers except Motion & Motion_Burst
SPI motion read
address-data delay
tSRAD-MOT
75
µs From rising SCLK for last bit of the address byte, to
falling SCLK for first bit of data being read. Applies to
0x02 Motion, and 0x50 Motion_Burst, registers
NCS to SCLK active tNCS-SCLK 120
SCLK to NCS inactive tSCLK-NCS 120
ns From NCS falling edge to first SCLK rising edge
ns From last SCLK falling edge to NCS rising edge, for
valid MISO data transfer
NCS to MISO high-Z tNCS-MISO
SROM download and tLOAD
10
frame capture byte-to-
byte delay
250
ns From NCS rising edge to MISO high-Z state
µs (see Figure 23 and 24)
NCS to burst mode tBEXIT
4
exit
µs Time NCS must be held high to exit burst mode
Transient Supply
IDDT
Current
85
mA Max supply current during a VDD3 ramp from 0 to 3.6V
11
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