ADP3088 Ver la hoja de datos (PDF) - Analog Devices
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ADP3088 Datasheet PDF : 11 Pages
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PRELIMINARY TECHNICAL DATA
low output inductance should be avoided to keep the PSM
threshold current at a desirably low level.
For the user's reference, when current is below the border-
line level, the duty ratio is modulated according to the for-
mula:
DD =
2
×
IO
×
VO +
VIN + VF
VF
− VSW
× fSW × L
VIN − VO − VSW
(10)
where the suffix indicates that the inductor current is dis-
continuous.
For controlling the capacitive component of the output
ripple voltage, the following constraint on the minimum
output capacitance should be applied:
CO
>
∆IL
8fSW ∆VR
(11)
where ∆VR is the tolerable ripple voltage. However, this
constraint is rarely relevant, as the typical capacitance re-
quirement is driven more by dynamic response require-
ments than by ripple concerns. In a typical application
circuit, a 10 µF capacitor produces a capacitive output
voltage ripple component of only about 2 mV. 10 µF is
usually sufficient for applications that do not impose par-
ticularly HF load transients, which imposes additional con-
straints that are elaborated upon in the next section.
Load Characterization
Optimization of the compensation, as well as the output
filter, requires some knowledge of a fundamental charac-
teristic of the load. Qualitatively, there are two types of
loads with which we are concerned: fast-slew-rate and
slow-slew-rate. These slew rates are assessed with respect
to the minimum [absolute] inductor [current] slew rate as
given by:
dI L
dt
, MIN
=<
VIN(MIN) − VSW
LMAX
− VO
and VO + VF
LMAX
(12)
where the "<" sign indicates a selection of whichever of the
bracketed terms is the lesser.
If the slew rate of the load is fast compared to the minimum
inductor slew rate, then the ability of the power converter
to contain the output voltage deviation following a load
change is limited not only by the response of the control
loop - i.e., by its speed to demand zero or maximum duty
ratio from the modulator - but by the power stage as well.
In such a case, beginning with the recognition that output
voltage deviation would be substantial even if the loop re-
sponse were instantaneous, it can be shown that one can
achieve better overall voltage containment by degenerating
the DC loop gain. As a technical matter, it should be noted
that there will always be some minimum output voltage
deviation downward due to a load step even if the inductor
slew is as fast as the load slew rate, because, during a
switching cycle, the modulator latches its "decision" to turn
off the switch and it cannot rescind that decision but must
wait for the next clock cycle to turn on the switch again and
ADP3088
begin slewing the inductor current upward. This is only a
second order consideration.
Slow slew rate loads may be referred to simply as conven-
tional loads, since these have been the more prevalent type
of load. Optimally compensating a conventional load is
synonymous with small signal AC considerations: the objec-
tive is to maximize the AC gain up to the crossover fre-
quency, ensure sufficient phase margin at the unity gain
crossover frequency, and keep the gain rolling off at higher
frequencies to avoid gain margin problems.
Fast slew rate loads may be referred to as digital loads
since, from the perspective of the power converter, they
have a digital characteristic when changing between two
extremes, and also because such fast slew rates tends to
characterize modern digital circuits, which often feature
power management interrupts - i.e., interrupt signals used
to turn on and off circuitry on an as-needed basis during
normal system operation. Optimally compensating a digital
load is more a task of impedance matching and DC gain
determination than a task of AC loop optimization.
Returning to constraints for choosing the output capacitor,
for digital loads another criteria for ensuring sufficient out-
put capacitance applies:
CO
>
2∆VO
∆IO2
dIL MIN
dt
(13)
where ∆IO is the maximum HF load step. It should be
noted that the formula results strictly from the physical
limitation of the output filter; the compensation must also
be optimized to maximize the response of the control loop
to avoid substantial additional output voltage deviation.
The formula might be also written in to describe a maxi-
mum inductance for a given capacitance, but it is generally
better practice to choose the inductor first and add capaci-
tance as needed.
The he impedance of the output capacitor together with a
digital load creates some limiting considerations, also. Se-
ries resistance (ESR) rather than capacitance can be a
dominant design consideration with non-MLC capacitors.
If the load is essentially digital, then the dynamic deviation
of the output voltage cannot be limited to any better than
the dynamic load current step times the ESR. In a for-
mula:
∆VO ≥ ∆IO × ESR
(14)
In such a case, it is often important to choose a capacitor
that controls the ESR to a sufficiently small value, and
MLC capacitors are often chosen to practically eliminate
the consideration of ESR entirely.
Closing the Loop - Compensation
The factors determining the response of the power con-
verter are noted: the feedback input resistor divider, a lead
network if applicable, the transconductance of the error
REV. PrK
–7–
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