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ADS-930 Datasheet PDF : 8 Pages
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®
®
ADS-930
DYNAMIC PERFORMANCE (Cont.)
MIN.
+25°C
TYP.
MAX.
0 to +70°C
MIN.
TYP. MAX.
–55 to +125°C
MIN. TYP.
MAX.
UNITS
Aperture Delay Time
Aperture Uncertainty
S/H Acquisition Time
( to ±0.003%FSR, 10V step)
Overvoltage Recovery Time
A/D Conversion Rate
—
±10
—
—
5
—
—
±10
—
—
5
—
—
±10
—
ns
—
5
—
ps rms
—
460
545
—
460
545
—
460
545
ns
—
600
1000
—
600
1000
—
600
1000
ns
500
—
—
500
—
—
500
—
—
kHz
ANALOG OUTPUT
Internal Reference
Voltage
Drift
External Current
+9.95
—
—
+10.0
±10
—
+10.05
—
1
+9.95
—
—
+10.0
±10
—
+10.05
—
1
+9.95
—
—
+10.0
±10
—
+10.05
—
1
Volts
ppm/°C
mA
DIGITAL OUTPUTS
Logic Levels
Logic "1"
Logic "0"
Logic Loading "1"
Logic Loading "0"
Delay, Falling Edge of ENABLE
to Output Data Valid
Output Coding
POWER REQUIREMENTS
+2.4
—
—
+2.4
—
—
+2.4
—
—
Volts
—
—
+0.4
—
—
+0.4
—
—
+0.4
Volts
—
—
–4
—
—
–4
—
—
–4
mA
—
—
+4
—
—
+4
—
—
+4
mA
—
—
10
—
—
10
—
—
10
ns
Complementary Offset Binary; Complementary Two's Complement, Offset Binary, Two's Complement
Power Supply Ranges
+15V Supply
–15V Supply
+5V Supply
Power Supply Currents
+15V Supply
–15V Supply
+5V Supply
Power Dissipation
Power Supply Rejection
+14.5
–14.5
+4.75
—
—
—
—
—
+15.0
–15.0
+5.0
+110
–100
+80
3.5
—
+15.5
–15.5
+5.25
+130
–125
+90
4.25
±0.02
+14.5
–14.5
+4.75
—
—
—
—
—
+15.0
–15.0
+5.0
+110
–100
+80
3.5
—
+15.5
–15.5
+5.25
+130
–125
+90
4.25
±0.02
+14.5
–14.5
+4.75
—
—
—
—
—
+15.0
–15.0
+5.0
+110
–100
+80
3.5
—
+15.5
–15.5
+5.75
+130
–125
+90
4.25
±0.02
Volts
Volts
Volts
mA
mA
mA
Watts
%FSR/%V
Footnotes:
All power supplies must be on before applying a start convert pulse. All
supplies and the clock (START CONVERT) must be present during warmup
periods. The device must be continuously converting during this time.
When COMP. BITS (pin 8) is low, logic loading "0" will be –350µA.
A 200ns wide start convert pulse is used for all production testing. For
applications requiring less than a 500kHz sampling rate, wider start convert
pulses can be used.
Effective bits is equal to:
Full Scale Amplitude
(SNR + Distortion) – 1.76 + 20 log
Actual Input Amplitude
6.02
TECHNICAL NOTES
1. Obtaining fully specified performance from the ADS-930
requires careful attention to pc-card layout and power
supply decoupling. The device's analog and digital
ground systems are connected to each other internally.
For optimal performance, tie all ground pins (4, 11, 13,
18, 24 and 30) directly to a large analog ground plane
beneath the package.
Bypass all power supplies and the +10V reference output
to ground with 4.7µF tantalum capacitors in parallel with
0.1µF ceramic capacitors. Locate the bypass capacitors
as close to the unit as possible.
2. The ADS-930 achieves its specified accuracies without
the need for external calibration. If required, the device's
small initial offset and gain errors can be reduced to zero
using the adjustment circuitry shown in Figure 2. When
using this circuitry, or any similar offset and gain calibra-
tion hardware, make adjustments following warmup. To
avoid interaction, always adjust offset before gain. Tie
pins 5 and 6 to ANALOG GROUND (pin 4) if not using
offset and gain adjust circuits.
3. Pin 8 (COMP. BITS) is used to select the digital output coding
format of the ADS-930. See Tables 3a and 3b. When this pin
has a TTL logic "0" applied, it complements all of the
ADS-930's digital outputs.
When pin 8 has a logic "1" applied and the ADS-930 is
operated within its unipolar (0 to –10V) input range, the output
coding is straight binary. Applying a logic "0" to pin 8 under
these conditions changes the output coding to complemen-
tary binary.
When pin 8 has a logic "1" applied and the ADS-930 is
operated within its bipolar (±5V) input range, the output coding
is offset binary. Applying a logic "0" to pin 8 under these
conditions changes the coding to complementary offset
binary. Using the MSB output (pin 40) instead of the MSB
output (pin 39) under these conditions changes the respective
output codings to two's complement and complementary two's
complement.
Pin 8 is TTL-compatible and can be directly driven with digital
logic in applications requiring dynamic control over its
function. There is an internal pull-up resistor on pin 8 allowing
3
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