ADT7318(RevPrN) Ver la hoja de datos (PDF) - Analog Devices

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ADT7318
(Rev.:RevPrN)

SPI/I2C® Compatible, 10-Bit Digital Temperature Sensor and Quad Voltage Output 12/10/8-Bit DAC

Analog Devices 

PRELIMINARY TECHNICAL DATA

ADT7316/7317/7318

IDD (Normal Mode)13

0.85

1.3

IDD (Power Down Mode) 1

3

0.5

1

Power Dissipation

tbd

tbd tbd

tbd

tbd tbd

mA

VIH = VDD and VIL = GND

µA

VDD = +4.5V to +5.5V, VIH=VDD and VIL=GND

µA

VDD = +2.7V to +3.6V, VIH=VDD and VIL=GND

µW

VDD = +2.7 V. Using Normal Mode

µW

VDD = +2.7 V. Using Shutdown Mode

Notes:

1 Temperature ranges are as follows: A Version: -40°C to +125°C.

2 See Terminology.

3 DC specifications tested with the outputs unloaded.

4 Linearity is tested using a reduced code range:; ADT7316 (code 115 to 4095); ADT7317 (code 28 to 1023); ADT7318 (code 8 to 255)

5 See Terminology.

6 Guaranteed by Design and Characterization, not production tested

7 In order for the amplifier output to reach its minimum voltage, Offset Error must be negative. In order for the amplifier output to reach its maximum voltage, VREF=VDD ,

"Offset plus Gain" Error must be positive.

8 The SDA & SCL timing is measured with the input filters turned on so as to meet the Fast-Mode I2C specification. Switching off the input filters improves the transfer

rate but has a negative affect on the EMC behaviour of the part.

9 Guaranteed by design. Not tested in production.

10 Guaranteed by design and characterization, not production tested.

11 All input signals are specified with tr = tf = 5 ns (10% to 90% of VDD) and timed from a voltage level of 1.6 V.

12 Measured with the load circuit of Figure 3.

13 IDD spec. is valid for all DAC codes. Interface inactive. All DACs active. Load currents excluded.

Specifications subject to change without notice.

DAC AC CHARACTERISTICS1

(VDD = +2.7V to +5.5 V; RL=4k7Ω to GND; CL=200pF to GND;

4K7Ω to VDD; All specifications TMIN to TMAX unless otherwise noted.)

Parameter2

Min Typ @ 25°C Max

Units Conditions/Comments

Output Voltage Settling Time

ADT7318

6

ADT7317

7

ADT7316

8

Slew Rate

0.7

Major-Code Change Glitch Energy

12

Digital Feedthrough

0.5

Digital Crosstalk

1

Analog Crosstalk

0.5

DAC-to-DAC Crosstalk

3

Multiplying Bandwidth

200

Total Harmonic Distortion

-70

NOTES

1Guaranteed by Design and Characterization, not production tested

2See Terminology

Specifications subject to change without notice.

VREF=VDD=+5V

8

µs

1/4 Scale to 3/4 Scale change (40 Hex to C0 Hex)

9

µs

1/4 Scale to 3/4 Scale change (100 Hex to 300 Hex)

10

µs

1/4 Scale to 3/4 Scale change (400 Hex to

C00 Hex)

V/µs

nV-s

1 LSB change around major carry.

nV-s

nV-s

nV-s

nV-s

kHz

dB

VREF=2V±0.1Vpp

VREF=2.5V±0.1Vpp. Frequency=10kHz.

t1

SCL

t4

t2

SDA

DATA IN

t3

SDA

DATA OUT

t5

t6

Figure 1. Diagram for I2C Bus Timing

–4–

REV. PrN

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