ADT7408CCPZ-REEL7(RevA) Ver la hoja de datos (PDF) - Analog Devices
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ADT7408CCPZ-REEL7 Datasheet PDF : 22 Pages
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ADT7408
Data Sheet
TIMING CHARACTERISTICS
TA = −20°C to +125°C, VDD = 3.0 V to 3.6 V, unless otherwise noted.
Table 2.
Parameter1
SCL Clock Frequency
Bus Free Time Between a Stop (P) and Start (S) Condition
Hold Time After (Repeated) Start Condition
Repeated Start Condition Setup Time
High Period of the SCL Clock
Low Period of the SCL Clock
Fall Time of Both SDA and SCL Signals
Rise Time of Both SDA and SCL Signals
Data Setup Time
Data Hold Time
Setup Time for Stop Condition
Capacitive Load for Each Bus Line, CB
Symbol
fSCL
tBUF
tHD:STA
tSU:STA
tHIGH
tLOW
tF
tR
tSU:DAT
tHD:DAT
tSU:STO
Min Typ Max Unit Test Conditions/Comments
10
100 kHz
4.7
μs
4.0
μs After this period, the first clock is generated.
4.7
μs
4.0
50 μs
4.7
μs
300 ns
1000 ns
250
ns
300
ns
4.0
μs
400 pF
1 Guaranteed by design and characterization, not production tested.
TIMING DIAGRAM
VIH
SCL
VIL
tHD:STA
VIH
SDA
tBUF
VIL
P
S
tR
tLOW
tR
tF
tHIGH
tHD:DAT
tF
tSU:DAT
tSU:STA
S
Figure 2. SMBus/I2C Timing Diagram
tSU:STO
P
Rev. A | Page 4 of 22
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