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ADT7408CCPZ-REEL7 Ver la hoja de datos (PDF) - Analog Devices

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ADT7408CCPZ-REEL7 Datasheet PDF : 24 Pages
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ADT7408
TIMING CHARACTERISTICS
TA = −20°C to +125°C, VDD = 3.0 V to 3.6 V, unless otherwise noted.
Table 2.
Parameter1
SCL Clock Frequency
Bus Free Time Between a Stop (P) and Start (S) Condition
Hold Time After (Repeated) Start Condition
Symbol
fSCL
tBUF
tHD:STA
Min Typ Max
10
100
4.7
4.0
Repeated Start Condition Setup Time
High Period of the SCL Clock
Low Period of the SCL Clock
Fall Time of Both SDA and SCL Signals
Rise Time of Both SDA and SCL Signals
Data Setup Time
Data Hold Time
Setup Time for Stop Condition
Capacitive Load for Each Bus Line, CB
tSU:STA
4.7
tHIGH
4.0
tLOW
4.7
tF
tR
tSU:DAT
250
tHD:DAT
300
tSU:STO
4.0
1 Guaranteed by design and characterization, not production tested.
50
300
1000
400
Unit Comments
kHz
μs
μs After this period, the first clock
is generated.
μs
μs
μs
ns
ns
ns
ns
μs
pF
TIMING DIAGRAM
VIH
SCL
VIL
tHD:STA
VIH
SDA
tBUF
VIL
P
S
tR
tLOW
tR
tF
tHIGH
tHD:DAT
tF
tSU:DAT
tSU:STA
S
Figure 2. SMBus/I2C Timing Diagram
tSU:STO
P
Rev. 0 | Page 4 of 24

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