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AIC1571

5-bit DAC, Synchronous PWM Power Regulator with Dual Linear Controllers

Analog Intergrations 

AIC1571

LUV

OC1

0.2V

+

SS

+

3.6V

OV

OVER CURRENT

LATCH

S

Q

R

INHIBIT

S

COUNTER

R

POR

FAULT LATCH

S

VCC

RQ

FAULT

Fig. 17 Simplified Schematic of Fault Logic

A simplified schematic is shown in figure 17. An

over-voltage detected on VSEN immediately

sets the fault latch. A sequence of three over-

current fault signals also sets the fault latch. An

under-voltage event on either linear output

(FB2 or FB3) is ignored until the soft-start inter-

val. Cycling the bias input voltage (+12V) off

then on reset the counter and the fault latch.

Over-Voltage Protection

During operation, a short on the upper PWM

MOSFET (Q1) causes VOUT1 to increase. When

the output exceed the over-voltage threshold of

115% of DACOUT, the FAULT pin is set to

fault latch and turns Q2 on as required in order

to regulate VOUT1 to 115% of DACOUT. The

fault latch raises the FAULT pin close to VCC

potential.

A separate over-voltage circuit provides pro-

tection during the initial application of power.

For voltage on VCC pin below the power-on re-

set (and above 4V), should VSEN exceed 0.7V,

the lower MOSFET (Q2) is driven on as need-

ed to regulate VOUT1 to 0.7V.

Over-Current Protection

All outputs are protected against excessive

over-current. The PWM controller uses upper

MOSFET’s on-resistance, RDS(ON) to monitor

the current for protection against shorted out-

puts. Both the linear regulator and controller

monitor FB2 and FB3 for under-voltage to pro-

tect against excessive current.

When the voltage across Q1 (ID•RDS(ON)) ex-

ceeds the level (200µA•ROCSET), this signal in-

hibit all outputs. Discharge soft-start capacitor

(Css) with 10µA current sink, and increments

the counter. Css recharges and initiates a soft-

start cycle again until the counter increments to

3. This sets the fault latch to disable all outputs.

Fig. 6 illustrates the over-current protection un-

til an over load on OUT1.

Should excessive current cause FB2 or FB3 to

fall below the linear under-voltage threshold,

the LUV signal sets the over-current latch if

Css is fully charged. Cycling the bias input

power off then on reset the counter and the

fault latch.

The over-current function for PWM controller

will trip at a peak inductor current (IPEAK) deter-

mined by:

IPEAK

=

IOCSET × ROCSET

RDS(ON)

The OC trip point varies with MOSFET’s tem-

perature. To avoid over-current tripping in the

normal operating load range, determine the

ROCSET resistor from the equation above with:

1. The maximum RDS(ON) at the highest junction.

2. The minimum IOCSET from the specification

11

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