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AIC1573

5-bit DAC, Synchronous PWM Power Regulator with Simple PWM Power Regulator, LDO And Linear Controller

Analog Intergrations 

AIC1573

Over-Current Protection

All outputs are protected against excessive over-

current. Both PWM controller uses upper

MOSFET’s on-resistance, RDS(ON) to monitor the

current for protection against shorted outputs. All

linear controllers monitor VSEN for under-voltage to

protect against excessive current.

When the voltage across Q1 (ID•RDS(ON)) exceeds

the level (200µA • ROCSET), this signal inhibit all

outputs. Discharge soft-start capacitor (Css) with

28µA current sink, and increments the counter.

Css recharges and initiates a soft-start cycle again

until the counter increments to 3. This sets the fault

latch to disable all outputs. Fig. 6 illustrates the

over-current protection until an over load on OUT1.

Should excessive current cause VSEN to fall below

the linear under-voltage threshold, the LUV signal

sets the over-current latch if Css is fully charged.

Cycling the bias input power (off then on reset the

counter and the fault latch.

The over-current function for PWM controller will trip

at a peak inductor current (IPEAK) determined by:

IPEAK = IOCSET × ROCSET

RDS(ON)

The OC trip point varies with MOSFET’s tempera-

ture. To avoid over-current tripping in the normal op-

erating load range, determine the ROCSET resistor

from the equation above with:

1. The maximum RDS(ON) at the highest junction.

2. The minimum IOCSET from the specification table.

3. Determine IPEAK > IOUT(MAX) + (inductor ripple

current) /2.

OUT1 Voltage Program

The output voltage of the PWM1 converter is pro-

grammed to discrete levels between 1.3V to 3.5V.

The VID pins program an internal voltage reference

(DACOUT) through a TTL compatible 5 bit digital to

analog converter. The VID pins can be left open for

a logic 1 input, because they are internally pulled

up to 5V by a 70kΩ resistor. Changing the VID in-

puts during operation is not recommended. ‘11111’

VID pin combinations disable the IC and open the

PGOOD pin.

OUT2 Voltage Selection

The AGP regulator output voltage is internally set to

one of two discrete levels, based on the SELECT

pin status. Left SELECT pin open, internal pulled

high, the output voltage is 3.3V. Grounding SE-

LECT pin will get the 1.5V output voltage.

The status of the SELECT pin can not be changed

during operation of the IC without immediatelly

causing a fault condition.

Shutdown

Neither PWM output switches until the soft-start

voltage exceeds the oscillator’s vally voltage. Addi-

tional, the reference on each linear’s amplifier is

clamped to the soft-start voltage. Holding the SS

pin low turns of all four regulators.

The VID codes resulting in an INHIBIT as shown in

Table 1 also shut down the IC.

Oscillator Synchronization

The AIC1573 avoids the problem of cross talk be-

tween the converters by way of phase control

method. Therefore, for both output voltage settings

less than 2.4V or both greater than 2.4V, PWM1

operates out of phase with PWM2. For one PWM

output voltage setting below 2.4V and the other

PWM output voltage setting of 2.4V and above,

PWM1 operates in phase with PWM2.

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