AIC809 Ver la hoja de datos (PDF) - Analog Intergrations
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AIC809 Datasheet PDF : 8 Pages
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AIC809/AIC810
PIN DESCRIPTIONS
GND Pin
: Ground.
RESET Pin (AIC809) : Active low output pin. RESET Output remains low while Vcc is below the reset
threshold.
RESET Pin (AIC810) : Active high output pin. RESET output remains high while Vcc is below the reset
threshold.
Vcc Pin
: Supply voltage.
DETAIL DESCRIPTIONS OF TECHNICAL TERMS
RESET OUTPUT
μP will be activated at a valid reset state. These
μP supervisory circuits assert reset to prevent
internal timer is activated after VCC returns
above the reset threshold, and RESET remains
low for the reset timeout period.
code execution errors during power-up,
BENEFITS OF HIGHLY ACCURATE RESET
power-down, or brownout conditions.
RESET is guaranteed to be a logic low for
THRESHOLD
AIC809/810 with specified voltage as 5V±10% or
VTH>VCC>0.9V. Once VCC exceeds the reset
threshold, an internal timer keeps RESET low
3V±10% are ideal for systems using a 5V±5% or
3V±5% power supply. The reset is guaranteed to
for the reset timeout period; after this interval,
RESET goes high.
assert after the power supply falls out of regulation,
but before power drops below the minimum
If a brownout condition occurs (VCC drops below
the reset threshold), RESET goes low. Any time
specified operating voltage range of the system
ICs. The pre-trimmed thresholds are reducing the
VCC goes below the reset threshold, the internal
range over which an undesirable reset may occur.
timer resets to zero, and RESET goes low. The
APPLICATION INFORMATION
NEGATIVE-GOING VCC TRANSIENTS
In addition to issuing a reset to the μP during
power-up, power-down, and brownout conditions,
AIC809 series are relatively resistant to
short-duration negative-going VCC transient.
ENSURING A VALID RESET OUTPUT DOWN
TO VCC=0
When VCC falls below 0.9V, AIC809 RESET
output no longer sinks current; it becomes an
open circuit. In this case, high-impedance CMOS
logic inputs connecting to RESET can drift to
undetermined voltages. Therefore, AIC809/810
with CMOS is perfect for most applications of VCC
below 0.9V. However in applications where
RESET must be valid down to 0V, adding a
pull-down resistor to RESET causes any leakage
currents to flow to ground, holding RESET low.
INTERFACING TO μP WITH BIDIRECTIONAL
RESET PINS
The RESET output on the AIC809N is open drain,
this device interfaces easily with μPs that have
bidirectional reset pins. Connecting the μ P
supervisor’s RESET output directly to the
microcontroller’s RESET pin with a single pull-up
resistor allows either device to assert reset.
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