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AK4552

3V 96kHz 24Bit ∆Σ CODEC

Asahi Kasei Microdevices 

ASAHI KASEI

[AK4552]

„ System Clock Input

OPERATION OVERVIEW

The relationship between the clock applied to the MCLK input and sampling rate is defined Table 1. The AK4552 detects

the changes of normal speed, double speed and quad speed automatically, ADC and DAC operation in Table 2 are decided

by inputted MCLK. In case of double speed, there are normal output and 1/2 decimation output in DAC. Selected 1/2

decimation, ADC outputs “L”, but not power-down. In case of 4 times speed, there are 1/2 decimation and 1/4 decimation

output in DAC, but not normal output. Selected 1/2 and 1/4 decimation, ADC outputs “L” but not power-down. The LRCK

clock input must be synchronized with MCLK, however the phase is not critical. *fs is sampling frequency.

Changed MCLK in operation, the AK4552 need not reset by PDN pin because the AK4552 detects the change of MCLK

automatically. But ADC and DAC may occur click noise until the clock is stable. However, if the clock may be stopped

when it is changed, the AK4552 is powered down.

All external clocks (MCLK, BCLK, LRCK) must be present unless PDN = “L”. If these clocks are not provided, the

AK4552 may draw excess current and may not possibly operate properly because the device utilizes dynamic refreshed

logic internally.

MCLK

64fs

96fs

128fs

192fs

256fs

384fs

512fs

768fs

Normal Speed Double Speed Quad Speed

(fs=44.1kHz) (fs=88.2kHz) (fs=176.4kHz)

N/A

N/A

11.2896MHz

N/A

N/A

16.9344MHz

N/A

11.2896MHz 22.5792MHz

N/A

16.9344MHz 33.8688MHz

11.2896MHz 22.5792MHz

N/A

16.9344MHz 33.8688MHz

N/A

22.5792MHz

N/A

N/A

33.8688MHz

N/A

N/A

Table 1. Master Clock Frequency Example

MCLK

Normal Speed

Double Speed

Quad Speed

64fs

ADC

DAC

N/A

N/A

N/A

“L” Output

N/A

1/4 Decimation

96fs

ADC

DAC

N/A

N/A

N/A

“L” Output

N/A

1/4 Decimation

128fs

ADC

DAC

N/A

N/A

“L” Output

1/2 Decimation

“L” Output

1/2 Decimation

192fs

ADC

DAC

N/A

N/A

“L” Output

1/2 Decimation

“L” Output

1/2 Decimation

256fs

ADC

DAC

O

O

O

N/A

O

N/A

384fs

ADC

DAC

O

O

O

N/A

O

N/A

512fs

ADC

DAC

O

O

N/A

N/A

N/A

N/A

768fs

ADC

DAC

O

O

N/A

N/A

N/A

N/A

Table 2. Master Clock Frequency & ADC/DAC Operation

* In Table 2, “O” mark is normal output, N/A is “Not Available”.

MS0055-E-01

-8-

2001/02

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