V53C16256SHK40 Ver la hoja de datos (PDF) - Mosel Vitelic Corporation
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V53C16256SHK40 Datasheet PDF : 19 Pages
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MOSEL VITELIC
The Self Refresh mode is terminated by returning
the RAS clock to a high level for a specified (tRPS)
minimum time. After termination of the Self Refresh
cycle normal accesses to the device may be initiat-
ed immediately, poviding that subsequest refresh
cycles utilize the CAS before RAS (CBR) mode of
operation.
Data Output Operation
The V53C16256SH Input/Output is controlled by
OE, CAS, WE and RAS. A RAS low transition en-
ables the transfer of data to and from the selected
row address in the Memory Array. A RAS high tran-
sition disables data transfer and latches the output
data if the output is enabled. After a memory cycle
is initiated with a RAS low transition, a CAS low
transition or CAS low level enables the internal I/O
path. A CAS high transition or a CAS high level dis-
ables the I/O path and the output driver if it is en-
abled. A CAS low transition while RAS is high has
no effect on the I/O data path or on the output driv-
ers. The output drivers, when otherwise enabled,
can be disabled by holding OE high. The OE signal
has no effect on any data stored in the output latch-
es. A WE low level can also disable the output driv-
ers when CAS is low. During a Write cycle, if WE
goes low at a time in relationship to CAS that would
normally cause the outputs to be active, it is neces-
sary to use OE to disable the output drivers prior to
the WE low transition to allow Data In Setup Time
(tDS) to be satisfied.
Power-On
After application of the VCC supply, an initial
pause of 200 µs is required followed by a minimum
of 8 initialization cycles (any combination of cycles
containing a RAS clock). Eight initialization cycles
are required after extended periods of bias without
clocks (greater than the Refresh Interval).
During Power-On, the VCC current requirement of
the V53C16256SH is dependent on the input levels
of RAS and CAS. If RAS is low during Power-On,
the device will go into an active cycle and ICC will ex-
hibit current transients. It is recommended that RAS
and CAS track with VCC or be held at a valid VIH dur-
ing Power-On to avoid current surges.
V53C16256SH
Table 1. V53C16256SH Data Output
Operation for Various Cycle Types
Cycle Type
I/O State
Read Cycles
CAS-Controlled Write
Cycle (Early Write)
WE-Controlled Write
Cycle (Late Write)
Read-Modify-Write
Cycles
Fast Page Mode Read
Fast Page Mode Write
Cycle (Early Write)
Fast Page Mode Read-
Modify-Write Cycle
RAS-only Refresh
CAS-before-RAS
Refresh Cycle
CAS-only Cycles
Data from Addressed
Memory Cell
High-Z
OE Controlled. High
OE = High-Z I/Os
Data from Addressed
Memory Cell
Data from Addressed
Memory Cell
High-Z
Data from Addressed
Memory Cell
High-Z
Data remains as in
previous cycle
High-Z
V53C16256SH Rev. 0.1 December 1998
17
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