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AM29DL400BB-120ED

4 Megabit (512 K x 8-Bit/256 K x 16-Bit) CMOS 3.0 Volt-only, Simultaneous Operation Flash Memory

Advanced Micro Devices 

The device features an Unlock Bypass mode to fa-

cilitate faster programming. Once a bank enters the

Unlock Bypass mode, only two write cycles are re-

quired to program a word or byte, instead of four.

The “Byte/Word Program Command Sequence” sec-

tion has details on programming data to the device

using both standard and Unlock Bypass command

sequences.

An erase operation can erase one sector, multiple

sectors, or the entire device. Tables 2 and 3 indicate

the address space that each sector occupies. The de-

vice address space is divided into two banks: Bank 1

contains the boot/parameter sectors, and Bank 2

contains the larger, code sectors of uniform size. A

“bank address” is the address bits required to

uniquely select a bank. Similarly, a “sector address”

is the address bits required to uniquely select a

sector.

If the system writes the autoselect command se-

quence, the device enters the autoselect mode. The

system can then read autoselect codes from the in-

ternal register (which is separate from the memory

array) on DQ7–DQ0. Standard read cycle timings

apply in this mode. Refer to the Autoselect Mode and

Autoselect Command Sequence sections for more

information.

ICC2 in the DC Characteristics table represents the

active current specification for the write mode. The

AC Characteristics section contains timing specifica-

tion tables and timing diagrams for write operations.

Simultaneous Read/Write Operations with

Zero Latency

This device is capable of reading data from one bank

of memory while programming or erasing in the

other bank of memory. An erase operation may also

be suspended to read from or program to another lo-

cation within the same bank (except the sector being

erased). Figure 19 shows how read and write cycles

may be initiated for simultaneous operation with

zero latency. ICC6 and ICC7 in the DC Characteristics

table represent the current specifications for read-

while-program and read-while-erase, respectively.

Standby Mode

When the system is not reading or writing to the de-

vice, it can place the device in the standby mode. In

this mode, current consumption is greatly reduced,

and the outputs are placed in the high impedance

state, independent of the OE# input.

The device enters the CMOS standby mode when the

CE# and RESET# pins are both held at VCC ± 0.3 V.

(Note that this is a more restricted voltage range

than VIH.) If CE# and RESET# are held at VIH, but

not within VCC ± 0.3 V, the device will be in the

standby mode, but the standby current will be

greater. The device requires standard access time

(tCE) for read access when the device is in either of

these standby modes, before it is ready to read data.

The device also enters the standby mode when the

RESET# pin is driven low. Refer to the next section,

“RESET#: Hardware Reset Pin”.

If the device is deselected during erasure or pro-

gramming, the device draws active current until the

operation is completed.

ICC3 in the DC Characteristics table represents the

standby current specification.

Automatic Sleep Mode

The automatic sleep mode minimizes Flash device

energy consumption. The device automatically en-

ables this mode when addresses remain stable for

tACC + 30 ns. The automatic sleep mode is indepen-

dent of the CE#, WE#, and OE# control signals.

Standard address access timings provide new data

when addresses are changed. While in sleep mode,

output data is latched and always available to the

system. ICC4 in the DC Characteristics table repre-

sents the automatic sleep mode current

specification.

RESET#: Hardware Reset Pin

The RESET# pin provides a hardware method of re-

setting the device to reading array data. When the

RESET# pin is driven low for at least a period of tRP,

the device immediately terminates any operation

in progress, tristates all output pins, and ignores all

read/write commands for the duration of the RE-

SET# pulse. The device also resets the internal state

machine to reading array data. The operation that

was interrupted should be reinitiated once the device

is ready to accept another command sequence, to

ensure data integrity.

Current is reduced for the duration of the RESET#

pulse. When RESET# is held at VSS±0.3 V, the device

draws CMOS standby current (ICC4). If RESET# is

held at VIL but not within VSS±0.3 V, the standby

current will be greater.

The RESET# pin may be tied to the system reset cir-

cuitry. A system reset would thus also reset the

Flash memory, enabling the system to read the

boot-up firmware from the Flash memory.

If RESET# is asserted during a program or erase op-

eration, the RY/BY# pin remains a “0” (busy) until

the internal reset operation is complete, which re-

quires a time of tREADY (during Embedded

Algorithms). The system can thus monitor RY/BY# to

determine whether the reset operation is complete.

If RESET# is asserted when a program or erase op-

eration is not executing (RY/BY# pin is “1”), the

reset operation is completed within a time of tREADY

(not during Embedded Algorithms). The system can

read data tRH after the RESET# pin returns to VIH.

Refer to the AC Characteristics tables for RESET#

parameters and to Figure 14 for the timing diagram.

Am29DL400B

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