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AM79C901A

HomePHY™ Single-Chip 1/10 Mbps Home Networking PHY

Advanced Micro Devices 

PRELIMINARY

LED_SPEED

LED_SPEED

Output

This output is designed to directly drive an LED. SPEED

low indicates that the HomePNA PHY is currently in the

high-speed mode. When operating in the 10BASE-T

mode this output will be held high.

LED_POWER

LED_POWER

Output

This output is designed to directly drive an LED.

POWER low indicates that the HomePNA PHY is cur-

rently in high-power mode. When operating in the

10BASE-T mode this output will be held high.

RESET

RESET

Input

The RESET is an active-low, asynchronous RESET

signal. This signal must be held low for a minimum of

5 µs and requires 60 µs for recovery after the rising

edge of RESET.

GPSI Interface

RXDAT

Receive Data

Output

RXDAT is the serial data received from the selected

port. Data on RXDAT is driven on the falling edge of

RXCLK.

RXCLK

Receive Data Clock

Output

RXCLK provides the timing reference for transfer of

the receive data. RXCLK is driven by the device and

operates at a maximum frequency of 10 MHz.

RXCRS

Receive Carrier Sense

Output

The RXCRS pin is active during receive or transmit ac-

tivity for the HomePNA PHY or during receive (based

on TBR17, bit 2) for the 10BASE-T PHY.

CLS

Collision

Output

This signal is asserted whenever a collision is detected

on the transmit and receive path of the selected port.

This signal will also be asserted for ~1 µs within 40 µs

after the negation of the TXEN signal in support of the

SQE test. The SQE functionality may be controlled via

TBR17, bit 11, and HPR16, bit 12.

TXDAT

Transmit Data

Input

TXDAT is the serial data driven from the MAC. Data on

TXDAT is latched on the falling edge of TXCLK.

TXCLK

Transmit Data Clock

Output

TXCLK provides the timing reference for transfer of the

transmitted data. TXCLK is driven by the device and

operates at a maximum frequency of 10 MHz.

TXEN

Transmit Enable

Input

TXEN indicates when the MAC device is presenting

valid transmit data on the TXDAT pin. TXEN must be

asserted with the first bit of preamble and remain as-

serted throughout the duration of the packet until it is

deasserted prior to the first TXCLK following the final

bit of the frame. TXEN transitions are synchronous to

TXCLK.

SPI Interface (Slave Mode Only)

SCLK

SPI Clock

Input

SCLK is driven from the controlling device as a timing

reference for transfer of information on the SDI and SDO

signals. The maximum clock frequency is 2.5 MHz.

CS

SPI Chip Select

Input

This pin is used to enable the Am79C901A for slave

mode transfers. When this pin is inactive (HIGH), the

device ignores SCLK and SDI inputs and holds SDO in

high-impedance.

SDI

SPI Serial Data In

Input

This data line provides input data from the master de-

vice to the Am79C901A. The data presented on this pin

is latched on the rising edge of SCLK.

SDO

SPI Serial Data Out

Output

This data line provides output data from the

Am79C901A to the master device. To provide for a ro-

bust interface, this data is driven on the rising edge of

SCLK.

MII Interface

RX_CLK

Receive Clock

Output

RX_CLK is a clock input that provides the timing ref-

erence for the transfer of the RX_DV, RXD[3:0], and

RX_ER signals from the Am79C901A device.

RX_CLK will provide a nibble rate clock. It operates

at a maximum frequency of 2.5 MHz.

Am79C901A

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