AM79C961KCW Ver la hoja de datos (PDF) - Advanced Micro Devices
Número de pieza
componentes Descripción
Lista de partido
AM79C961KCW Datasheet PDF : 173 Pages
| |||
PRELIMINARY
SD[0-15]
BPCS
PRDB[0-7]
16-Bit
System
Data
PRDB[0]/EESK
PCnet-ISA+
Controller
PRDB[1]/EEDI
PRDB[2]/EEDO
24-Bit
System
Address
SA[0-19]
LA[17-23]
EECS
IRQ15/APCS IRQ12/FlashWE SHFBUSY
ISA
Bus
VCC
AMD
A[0-4]
D[0-7]
IEEE
Address
PROM
G
A[0-15]
WE
D[0-7]
Flash
OE
CS
SK
DI EEPROM
DO
VCC
CS
ORG
Bus Master Block Diagram
Plug and Play Compatible with Flash Support
18183B-7
Shared Memory Mode
System Interface
The Shared Memory mode is the other fundamental op-
erating mode available on the PCnet-ISA+ controller.
The PCnet-ISA+ controller uses the same descriptor and
buffer architecture as the LANCE, but these data struc-
tures are stored in static RAM controlled by the
PCnet-ISA+ controller. The static RAM is visible as a
memory resource to the PC. The other resources look
the same as in the Bus Master mode.
The Boot PROM is selected by an external device which
drives the Boot PROM Address Match (BPAM) input to
the PCnet-ISA+ controller. The PCnet-ISA+ controller
can perform two 8-bit accesses from the 8-bit Boot
PROM and presents 16-bits of data. The shared mem-
ory works the same way, with an external device
generating Shared Memory Address Match and the
PCnet-ISA+ controller performing the read or write and
the 8 to 16-bit data conversion.
Converting shared memory accesses from 8-bit cycles
to 16-bit cycles allows use of the much faster 16-bit cy-
cle timing while cutting the number of bus cycles in half.
This raises performance to more than 400% of what
could be achieved with 8-bit cycles. Converting boot
PROM accesses to 16-bit cycles allows the two memory
resources to be in the same 128 Kbyte block of memory
without a clash between two devices with different data
widths.
The PCnet-ISA+ controller uses an internal address
comparator to perform SRAM prefetches on the Private
Data Bus; the SA0-15 signals are used internally to de-
termine whether a SRAM read cycle prefetch is a match
or a miss.
Access to the Ethernet controller registers, board con-
figuration registers, and Address PROM is done with
on-chip address comparators.
Network Interface
The PCnet-ISA+ controller can be connected to an IEEE
802.3 network via one of two network interface ports.
The Attachment Unit Interface (AUI) provides an IEEE
802.3 compliant differential interface to a remote MAU
or an on-board transceiver. The 10BASE-T interface
provides a twisted-pair Ethernet port. The PCnet-ISA+
controller provides three modes of network interface
Am79C961
1-505
Share Link: 