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AM79C961AKCW

PCnet™-ISA II Jumperless, Full Duplex Single-Chip Ethernet Controller for ISA

Advanced Micro Devices 

PIN DESCRIPTION: BUS MASTER MODE

These pins are part of the bus master mode. In order to

understand the pin descriptions, definition of some

terms from a draft of IEEE P996 are included.

IEEE P996 Terminology

Alternate Master: Any device that can take control of

the bus through assertion of the MASTER signal. It has

the ability to generate addresses and bus control sig-

nals in order to perform bus operations. All Alternate

Masters must be 16 bit devices and drive SBHE.

Bus Ownership: The Current Master possesses bus

ownership and can assert any bus control, address and

data lines.

Current Master: The Permanent Master, Temporary

Master or Alternate Master which currently has owner-

ship of the bus.

Permanent Master: Each P996 bus will have a device

known as the Permanent Master that provides certain

signals and bus control functions as described in Sec-

tion 3.5 (of the IEEE P996 spec.), “Permanent Master”.

The Permanent Master function can reside on a Bus

Adapter or on the backplane itself.

Temporary Master: A device that is capable of gener-

ating a DMA request to obtain control of the bus and

directly asserting only the memory and I/O strobes

during bus transfer. Addresses are generated by the

DMA device on the Permanent Master.

ISA Interface

AEN

Address Enable

Input

This signal must be driven LOW when the bus performs

an I/O access to the device.

BALE

Used to latch the LA20–23 address lines.

DACK 3, 5-7

DMA Acknowledge

Input

Asserted LOW when the Permanent Master acknowl-

edges a DMA request. When DACK is asserted the

PCnet-ISA II controller becomes the Current Master by

asserting the MASTER signal.

DRQ 3, 5-7

DMA Request

Input/Output

When the PCnet-ISA II controller needs to perform a

DMA transfer, it asserts DRQ. The Permanent Master

acknowledges DRQ with the assertion of DACK. When

the PCnet-ISA II does not need the bus it desserts

DRQ. The PCnet-ISA II provides for fair bus bandwidth

sharing between two bus mastering devices on the ISA

bus through an adaptive delay which is inserted

between back-to-back DMA requests. See the

Back-to-Back DMA Requests section for details.

Because of the operation of the Plug and Play regis-

ters, the DMA Channels on the PCnet-ISA II must be

attached to the specific DRQ and DACK signals on the

PC/AT bus as indicated by the pin names.

IOCHRDY

I/O Channel Ready

Input/Output

When the PCnet-ISA II controller is being accessed,

IOCHRDY HIGH indicates that valid data exists on the

data bus for reads and that data has been latched for

writes. When the PCnet-ISA II controller is the Current

Master on the ISA bus, it extends the bus cycle as long

as IOCHRDY is LOW.

IOCS16

I/O Chip Select 16

Output

When an I/O read or write operation is performed, the

PCnet-ISA II controller will drive the IOCS16 pin LOW

to indicate that the chip supports a 16-bit operation at

this address. (If the motherboard does not receive this

signal, then the motherboard will convert a 16-bit

access to two 8-bit accesses).

The PCnet-ISA II controller follows the IEEE P996 spec-

ification that recommends this function be implemented

as a pure decode of SA0-9 and AEN, with no depen-

dency on IOR, or IOW; however, some PC/AT clone sys-

tems are not compatible with this approach. For this

reason, the PCnet-ISA II controller is recommended to

be configured to run 8-bit I/O on all machines. Since data

is moved by memory cycles there is virtually no perfor-

mance loss incurred by running 8-bit I/O and compatibil-

ity problems are virtually eliminated. The PCnet-ISA II

controller can be configured to run 8-bit-only I/O by

clearing Bit 0 in Plug and Play register F0.

IOR

I/O Read

Input

IOR is driven LOW by the host to indicate that an Input/

Output Read operation is taking place. IOR is only valid

if the AEN signal is LOW and the external address

matches the PCnet-ISA II controller’s predefined I/O

address location. If valid, IOR indicates that a slave

read operation is to be performed.

IOW

I/O Write

Input

IOW is driven LOW by the host to indicate that an Input/

Output Write operation is taking place. IOW is only valid

if AEN signal is LOW and the external address matches

the PCnet-ISA II controller’s predefined I/O address

location. If valid, IOW indicates that a slave write oper-

ation is to be performed.

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