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AM79C961AKCW

PCnet™-ISA II Jumperless, Full Duplex Single-Chip Ethernet Controller for ISA

Advanced Micro Devices 

PRDB1/EEDI

Private Data Bus Bit 1/Data In Input/Output

A multifunction pin which serves as PRDB1 of the

private data bus and, when ISACSR3 bit 4 is set,

changes to become DATA In to the EEPROM.

PRDB0/EESK

Private Data Bus Bit 0/

Serial Clock

Input/Output

A multifunction pin which serves as PRDB0 of the

private data bus and, when ISACSR3 bit 4 is set,

changes to become Serial Clock to the EEPROM.

SHFBUSY

Shift Busy

Input/Output

This pin indicates that a read from the external

EEPROM is in progress. It is active only when data is

being shifted out of the EEPROM due to a hardware

RESET or assertion of the EE_LOAD bit (ISACSR3, bit

14). If this pin is left unconnected or pulled low with a

pull-down resistor, an EEPROM checksum error is

forced. Normally, this pin should be connected to VCC

through a 10K Ω pull-up resistor.

EECS

EEPROM CHIP SELECT

Output

This signal is asserted when read or write accesses

are being performed to the EEPROM. It is controlled by

ISACSR3. It is driven at Reset during EEPROM Read.

SLEEP

Sleep

Input

When SLEEP input is asserted (active LOW), the PC-

net-ISA II controller performs an internal system reset

and proceeds into a power savings mode. All outputs

will be placed in their normal reset condition. All PC-

net-ISA II controller inputs will be ignored except for the

SLEEP pin itself. Deassertion of SLEEP results in the

device waking up. The system must delay the starting

of the network controller by 0.5 seconds to allow inter-

nal analog circuits to stabilize.

SMA

Slave Mode Architecture

Input

This pin must be permanently pulled LOW for operation

in the Bus Slave mode. It is sampled after the hardware

RESET sequence. In the Bus Slave mode, the PC-

net-ISA II can be programmed for Shared Memory ac-

cess or Programmed I/O access through the PIOSEL

bit (ISACSR2, bit 13).

SMAM

Shared Memory

Address Match

Input

When the Shared Memory architecture is selected

(ISACSR2, bit 13), this pin is an input that indicates an

access to shared memory when asserted. The type of

access is decided by MEMR or MEMW.

When the Programmed I/O architecture is selected,

this pin should be permanently tied HIGH.

SROE

Static RAM Output Enable

Output

This pin directly controls the external SRAM’s OE pin.

SRCS/IRQ12

Static RAM Chip Select

Output

This pin directly controls the external SRAM’s chip

select (CS) pin when the Flash boot ROM option is

selected.

When Flash boot ROM option is not selected, this pin

becomes IRQ12.

SRWE/WE

Static RAM Write Enable/

Write Enable

Output

This pin (SRWE) directly controls the external SRAM’s

WE pin when a Flash memory device is not

implemented.

When a Flash memory device is implemented, this pin

becomes a global write enable (WE) pin.

XTAL1

Crystal Connection

Input

The internal clock generator uses a 20 MHz crystal that

is attached to pins XTAL1 and XTAL2. Alternatively, an

external 20 MHz CMOS-compatible clock signal can be

used to drive this pin. Refer to the section on External

Crystal Characteristics for more details.

XTAL2

Crystal Connection

Output

The internal clock generator uses a 20 MHz crystal that

is attached to pins XTAL1 and XTAL2. If an external

clock is used, this pin should be left unconnected.

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Am79C961A

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