AM79C971 Ver la hoja de datos (PDF) - Advanced Micro Devices

Número de pieza

componentes Descripción

Lista de partido

AM79C971

PCnet™-FAST Single-Chip Full-Duplex 10/100 Mbps Ethernet Controller for PCI Local Bus

Advanced Micro Devices 

INTA

Interrupt Request

Output

An attention signal which indicates that one or more of

the following status flags is set: BABL, EXDINT, IDON,

JAB, MERR, MISS, MFCO, MPINT, RCVCCO, RINT,

SINT, SLPINT, TINT, TXSTRT, UINT, MCCIINT, MC-

CINT, MPDTINT, MAPINT, MREINT, and STINT. Each

status flag has either a mask or an enable bit which al-

lows for suppression of INTA assertion. Table 1 shows

the flag meanings.

Table 1. Interrupt Flags

Name

BABL

EXDINT

IDON

JAB

MERR

MISS

MFCO

MPINT

RCVCCO

RINT

SLPINT

SINT

TINT

TXSTRT

UINT

MCCIINT

MCCINT

MPDTINT

Description Mask Bit

Babble

CSR3, bit 14

Excessive

Deferral

CSR5, bit 6

Initialization

Done

CSR3, bit 8

Jabber

CSR4, bit 0

Memory Error CSR3, bit 11

Missed Frame CSR3, bit 12

Missed Frame

Count Over- CSR4, bit 8

flow

Magic Packet

Interrupt

CSR5, bit 3

Receive

Collision Count CSR4, bit 4

Overflow

Receive

Interrupt

CSR3, bit 10

Sleep Interrupt CSR5, bit 8

System Error CSR5, bit 10

Transmit

Interrupt

CSR3, bit 9

Transmit Start CSR4, bit 2

User Interrupt CSR4, bit 7

Internal MII

Management

Command

Complete

Interrupt

CSR7, bit 2

MII

Management

Command

Complete

Interrupt

CSR7, bit 4

MII PHY Detect

Transition

CSR7, bit 0

Interrupt

Interrupt Bit

CSR0, bit 14

CSR5, bit 7

CSR0, bit 8

CSR4, bit 1

CSR0, bit 11

CSR0, bit 12

CSR4, bit 9

CSR5, bit 4

CSR4, bit 5

CSR0, bit 10

CSR5, bit 9

CSR5, bit 11

CSR0, bit 9

CSR4, bit 3

CSR4, bit 6

CSR7, bit 3

CSR7, bit 5

CSR7, bit 1

Table 1. Interrupt Flags

Name

MAPINT

MREINT

STINT

Description Mask Bit Interrupt Bit

MII Auto-Poll

Interrupt

CSR7, bit 6

CSR7, bit 7

MII

Management

Frame Read

CSR7, bit 8

Error Interrupt

CSR7, bit 9

Software Timer

Interrupt

CSR7, bit 10

CSR7, bit 11

By default INTA is an open-drain output. For applica-

tions that need a high-active edge-sensitive interrupt

signal, the INTA pin can be configured for this mode by

setting INTLEVEL (BCR2, bit 7) to 1.

When RST is active, INTA is the output for NAND tree

testing.

IRDY

Initiator Ready

Input/Output

IRDY indicates the ability of the initiator of the transac-

tion to complete the current data phase. IRDY is used

in conjunction with TRDY. Wait states are inserted until

both IRDY and TRDY are asserted simultaneously. A

data phase is completed on any clock when both IRDY

and TRDY are asserted.

When the Am79C971 controller is a bus master, it as-

serts IRDY during all write data phases to indicate that

valid data is present on AD[31:0]. During all read data

phases, the device asserts IRDY to indicate that it is

ready to accept the data.

When the Am79C971 controller is the target of a trans-

action, it checks IRDY during all write data phases to

determine if valid data is present on AD[31:0]. During

all read data phases, the device checks IRDY to deter-

mine if the initiator is ready to accept the data.

When RST is active, IRDY is an input for NAND tree

testing.

PAR

Parity

Input/Output

Parity is even parity across AD[31:0] and C/BE[3:0].

When the Am79C971 controller is a bus master, it gen-

erates parity during the address and write data phases.

It checks parity during read data phases. When the

Am79C971 controller operates in slave mode, it checks

parity during every address phase. When it is the target

of a cycle, it checks parity during write data phases and

it generates parity during read data phases.

When RST is active, PAR is an input for NAND tree

testing.

Am79C971

19

Share Link: