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AM79C978 Ver la hoja de datos (PDF) - Advanced Micro Devices

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AM79C978 Datasheet PDF : 261 Pages
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n Independent internal TX and RX FIFOs
— Programmable FIFO watermarks for both TX
and RX operations
— RX frame queuing for high latency PCI bus
host operation
— Programmable allocation of buffer space
between RX and TX queues
n Extensive programmable internal/external
loopback capabilities
n EEPROM interface supports jumperless design
and provides through-chip programming
— Supports full programmability of half-/full-
duplex operation through EEPROM mapping
— Programmable PHY reset output pin capable
of resetting external PHY without the need
for buffering
n Extensive programmable LED status support
n Look-Ahead Packet Processing (LAPP) data
handling technique reduces system overhead
by allowing protocol analysis to begin before
the end of a receive frame
n Includes Programmable Inter Packet Gap (IPG)
to address less network aggressive MAC
controllers
n Offers the Modified Back-Off algorithm to
address the Ethernet Capture Effect
n IEEE 1149.1-compliant JTAG Boundary Scan
test access port interface and NAND tree test
mode for board-level production connectivity
test
n Software compatible with AMD’s PCnet™
Family and LANCE/C-LANCE register and
descriptor architecture
n Very low power consumption
n +3.3 V power supply along with 5 V tolerant I/Os
enable broad system compatibility
n Available in 144-pin TQFP and 160-pin PQFP
packages
GENERAL DESCRIPTION
The Am79C978 controller is the first in a series of home
networking products from AMD. The Am79C978 con-
troller is fabricated in an advanced low power 3.3 V
CMOS process to provide low operating current for
power sensitive applications.
The Am79C978 controller contains an Ethernet Con-
troller based on the Am79C971 Fast Ethernet control-
ler, a physical layer device for supporting the 802.3
standard for 10BASE-T, and a physical layer device for
data networking at speeds up to 1 Mbps over ordinary
residential telephone wiring.
The integrated PCI Ethernet controller is a highly inte-
grated 32-bit full-duplex, 10/100 Mbps Ethernet con-
troller solution designed to address high-performance
system application requirements. It is a flexible bus-
mastering device that can be used in any application,
including network ready PCs. The bus master architec-
ture provides high data throughput and low CPU and
system bus utilization.
The integrated Ethernet transceiver is a physical layer
device supporting the IEEE 802.3 standards for
10BASE-T. It provides all of the PHY layer functions re-
quired to support 10 Mbps data transfer speeds.
The integrated HomePNA transceiver is a physical
layer device that enables data networking at speeds up
to 1 Mbps over common residential phone wiring re-
gardless of topology and without disrupting telephone
(POTS) service.
The 32-bit multiplexed bus interface unit provides a di-
rect interface to the PCI local bus, simplifying the de-
sign of an Ethernet or home network node in a PC
system. The device has built-in support for both little
and big endian byte alignment. The integrated home
networking controller’s advanced CMOS design allows
the bus interface to be connected to either a +5.0 V or
a +3.3 V signaling environment. A compliant IEEE
1149.1 JTAG test interface for board level testing is
also provided, as well as a NAND tree test structure for
those systems that do not support the JTAG interface.
The integrated Am79C978 home networking controller
is also compliant with the PC98 and Net PC specifica-
tions. It includes the full implementation of the Mi-
crosoft OnNow and ACPI specifications, which are
backward compatible with Magic Packet technology. It
is also compliant with the PCI Bus Power Management
Interface specification by supporting the four power
management states (D0, D1, D2, and D3), the optional
PME pin, and the necessary configuration and data
registers.
The integrated Am79C978 home networking controller
is a complete Ethernet or home network node inte-
grated into a single VLSI device. It contains a bus inter-
face unit, a Direct Memory Access (DMA) Buffer
Management Unit, an ISO/IEC 88023 (IEEE 802.3)
compliant Media Access Controller (MAC), a Transmit
FIFO and a large Receive FIFO, and an IEEE 802.3u
compliant MII. Both IEEE 802.3 compliant full-duplex
and half-duplex operations are supported on the MII in-
terface. 10/100 Mbps operation is supported through
the MII interface.
The integrated Am79C978 home networking controller
is register compatible with the LANCE (Am7990) and
C-LANCE (Am79C90) Ethernet controllers and all
2
Am79C978

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