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AM79C978AKCW

PCnet™- Home Single-Chip 1/10 Mbps PCI Home Networking Controller

Advanced Micro Devices 

BASIC FUNCTIONS

System Bus Interface

The Am79C978A controller is designed to operate as a

bus master during normal operations. Some slave I/O

accesses to the Am79C978A controller are required in

normal operations as well. Initialization of the

Am79C978A controller is achieved through a combina-

tion of PCI Configuration Space accesses, bus slave

accesses, bus master accesses, and an optional read

of a serial EEPROM that is performed by the

Am79C978A controller. The EEPROM read operation

is performed through the 93C46 EEPROM interface.

The ISO 8802-3 (IEEE/ANSI 802.3) Ethernet Address

may reside within the serial EEPROM. Some controller

configuration registers may also be programmed by the

EEPROM read operation.

The Address PROM, on-chip board-configuration reg-

isters, and the Ethernet controller registers occupy 32

bytes of address space. I/O and memory mapped I/O

accesses are supported. Base Address registers in the

PCI configuration space allow locating the address

space on a wide variety of starting addresses.

Software Interface

The software interface to the Am79C978A controller is

divided into three parts. One part is the PCI configura-

tion registers used to identify the Am79C978A control-

ler and to setup the configuration of the device. The

setup information includes the I/O or memory mapped

I/O base address, mapping of the Expansion ROM,

and the routing of the Am79C978A controller interrupt

channel. This allows for a jumperless implementation.

The second portion of the software interface is the di-

rect access to the I/O resources of the Am79C978A

controller. The Am79C978A controller occupies 32

bytes of address space that must begin on a 32-byte

block boundary. The address space can be mapped

into I/O or memory space (memory mapped I/O). The

I/O Base Address Register in the PCI Configuration

Space controls the start address of the address space

if it is mapped to I/O space. The Memory Mapped I/O

Base Address Register controls the start address of

the address space if it is mapped to memory space.

The 32-byte address space is used by the software to

program the Am79C978A controller operating mode,

to enable and disable various features, to monitor op-

erating status, and to request particular functions to

be executed by the Am79C978A controller.

The third portion of the software interface is the

descriptor and buffer areas that are shared be-

tween the software and the Am79C978A controller

during normal network operations. The descriptor

area boundaries are set by the software and do not

change during normal network operations. There

is one descriptor area for receive activity, and

there is a separate area for transmit activity. The

descriptor space contains relocatable pointers to

the network frame data, and it is used to transfer

frame status from the Am79C978A controller to the

software. The buffer areas are locations that hold

frame data for transmission or that accept frame

data that has been received.

Network Interfaces

The Am79C978A controller provides all of the PHY

layer functions for 10 Mbps (10BASE-T) or 1 Mbps.

The Am79C978A controller supports both half-duplex

and full-duplex operation on the network MII interface.

Media Independent Interface

The Am79C978A controller fully supports the MII ac-

cording to the IEEE 802.3 standard. This Reconcilia-

tion Sublayer interface allows a variety of PHYs

(100BASE-TX, 100BASE-FX, 100BASE-T4,

100BASE-T2, 10BASE-T, etc.) to be attached to the

Am79C978A device without future upgrade problems.

The MII interface is a 4-bit (nibble) wide data path in-

terface that runs at 25 MHz for 100-Mbps networks or

2.5 MHz for 10-Mbps networks. The interface consists

of two independent data paths, receive (RXD(3:0))

and transmit (TXD(3:0)), control signals for each data

path (RX_ER, RX_DV, TX_EN), network status sig-

nals (COL, CRS), clocks (RX_CLK, TX_CLK) for each

data path, and a two-wire management interface

(MDC and MDIO). See Figure 1.

MII Transmit Interface

The MII transmit clock is generated by the external

PHY and is sent to the Am79C978A controller on

the TX_CLK input pin. The clock can run at 25 MHz

or 2.5 MHz, depending on the speed of the net-

work to which the external PHY is attached. The

data is a nibble-wide (4 bits) data path, TXD(3:0),

from the Am79C978A controller to the external

PHY and is synchronous to the rising edge of

TX_CLK. The transmit process starts when the

Am79C978A controller asserts the TX_EN, which

indicates to the external PHY that the data on

TXD(3:0) is valid.

Normally, unrecoverable errors are signaled through

the MII to the external PHY with the TX_ER output pin.

The external PHY will respond to this error by generat-

ing a TX coding error on the current transmitted frame.

The Am79C978A controller does not use this method

of signaling errors on the transmit side. The

Am79C978A controller will invert the FCS on the last

byte generating an invalid FCS. The TX_ER pin should

be tied to GND.

Am79C978A

29

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