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AM79C970A

PCnet™-PCI II Single-Chip Full-Duplex Ethernet Controller for PCI Local Bus Product

Advanced Micro Devices 

read operation will always happen automatically after

the deassertion of the RST pin. In addition, the host can

start the read operation by setting the PREAD bit

(BCR19, bit 14). While the EEPROM read is on-going,

the PCnet-PCI II controller will disconnect any slave

access where it is the target by asserting STOP to-

gether with DEVSEL, while driving TRDY high. STOP

will stay asserted until the host removes FRAME.

Note that I/O and memory slave accesses will only be

disconnected if they are enabled by setting the IOEN or

MEMEN bit in the PCI Command register. Without the

enable bit set, the cycles will not be claimed at all.

Since H_RESET clears the IOEN and MEMEN bits, for

the automatic EEPROM read after H_RESET the dis-

connect only applies to configuration cycles.

A second situation where the PCnet-PCI II controller

will generate a PCI disconnect/retry cycle is when the

host tries to access any of the I/O resources right after

having read the Reset register. Since the access gen-

erates an internal reset pulse of about 1 µs in length, all

further slave accesses will be deferred until the internal

reset operation is completed.

CLK

1

2

3

4

5

FRAME

AD

ADDR

DATA

C/BE

CMD

BE

PAR

PAR

PAR

IRDY

TRDY

DEVSEL

STOP

Figure 6. Disconnect Of Slave Cycle When Busy

19436C-9

Am79C970A

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