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AMD-750

Chipset

Advanced Micro Devices 

23016A—August 1999

AMD-750™ Chipset Overview

n Decoupled and burst DRAM refresh with staggered CS

timing

n Provides the following refresh options:

• Programmable refresh rate

• CAS-before-RAS

• Populated banks only

• Chipset powerdown via SDRAM automatic refresh

command

• Automatic refresh of idle slots—improves bus

availability for memory access by the processor or

system

PCI Bus Controller

The PCI bus controller has the following features:

n Compliance with PCI Local Bus Specification, Revision 2.2

n Supports six PCI masters

n 32-bit interface, compatible with 3.3-V and 5-V PCI I/O

n Synchronous PCI bus operation up to 33 MHz

n PCI-initiator peer concurrence

n Automatic processor-to-PCI burst cycle detection

n Four-entry, 64-bit PCI master (processor or AGP) write FIFO

n Extensive utilization of FIFOs

n Zero wait-state PCI initiator and target burst transfers

n PCI-to-DRAM data streaming up to 132 Mbytes per second

n Enhanced PCI command optimization, such as memory read

line (MRL), memory read multiple (MRM), and

memory-write-and-invalidate (MWI)

n Timer-enforced fair arbitration between PCI initiators

n Supports advanced concurrency

n Supports retry disconnect for improved bus utilization

n PCI read buffer keeps track of each master

n PCI target request queue

AMD-751™ System Controller

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