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AN1816

USING THE HC912B32 TO IMPLEMENT THE DISTRIBUTED SYSTEMS INTERFACE (DSI) PROTOCOL

Freescale Semiconductor 

Application Note

Freescale Semiconductor, Inc.

Master Board

8

Figure 8 Top Level DSI System Connections shows how the ICs are

connected together. It should be noted that the diagram shows a daisy

chain connected slave but slave nodes can also be connected onto the

bus in parallel. The parallel configuration is used for slave nodes that

have pre-programmed addresses. The SPI of the HC912B32 is set up

such that it acts as the master and all communication from the

HC912B32 to the MC68HC55 is via the SPI. The MC33790, the physical

layer interface to the DSI bus, sends commands to and receives

responses from the slave devices.

Software required to control the system can be programmed into the

HC912B32’s 32k of FLASH memory. It also has 768 bytes of EEPROM

and 1k of RAM. The PWM is used to provide the MC68HC55 with a

system clock. It is set up such that PWM channel 0 is output on port P

pin 0 (PP0) and connected to the SCLK pin of the MC68HC55 SPI

Peripheral. The HC912B32’s on board SPI is a key element in the DSI

communication protocol and is set up as follows. The MOSI, MISO and

SCLK pins on the HC912B32 are connected to the MC68HC55’s DI, DO,

CLK pins respectively. Port S pin 7 (PS7) is connected to the CS pin on

the MC68HC55. It should then be defined in the software as a

general-purpose I/O pin and set up to drive CS on the MC68HC55. CS

is an active low signal that is controlled by the HC912B32. When driven

low it indicates the start of message transmission from the HC912B32 to

the MC68HC55 and in turn to the MC33790 and then to the slave nodes.

This is the start of what is termed a SPI burst transfer (refer to the sub

section: ‘Initialisation of the PWM and SPI’ in the Software Design

section of this Application Note). The end of a SPI burst transfer is

signalled by the HC912B32 pulling CS high. Commands are sent to and

responses are received from the slave nodes via the SPI during a burst

transfer. The data written to the SPI data register is transferred into the

MC68HC55’s data register, which transmits the message to the slave

nodes via the MC33790 Bus Transceiver.

The MC68HC55 is the protocol controller of the system and controls all

the digital functions of the DSI. It contains 2 independent DSI channels,

each capable of interfacing to up to 15 slave nodes. The MC68HC55 SPI

Peripheral uses 3 pins to transmit a message to the MC33790 Bus

Transceiver. Pin DSIxS (signal) on the MC68HC55 transmits the data

output signal to the MC33790. Data bits on this signal line are pulse

length encoded voltage levels. A logic zero starts with a falling edge on

DSIxS and is low for two thirds of the bit time and then high for one third

of the bit time. A logic one starts with a falling edge on DSIxS and is low

for one third of the bit time and then high for two thirds of the bit time.

DSIxF (frame) output pin idles high and is driven low during each

transfer frame. DSIxR is the data input signal from the MC33790. The

MC68HC55 samples the CMOS level on this pin at the end of a bit time.

This level corresponds to the current sensed by the MC33790.

AN1816

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