AN18208A Ver la hoja de datos (PDF) - Panasonic Corporation
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AN18208A Datasheet PDF : 37 Pages
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AN18208A
Technical Data (continued)
y I2C-bus interface (continued)
8. Precaution in setup of I2C-bus data
1) Power on
a) All data must be set on IC when the power supply is tuned on. (SUB ADD : 00H to 07H)
b) IF limit amplifier must be ON at the time of the initial data transfer of I2C. (SUB ADD : 04H, D7 = "1")
c) The power supply transition time (VCC1, 2 = 0 → 9 V) must be more than 10 ms.
d) Electric current flows in the power supply off condition when a power supply is connected to the TUNED terminal
(Pin 21). Therefore, be careful in the case of the backup mode such as a microcomputer.
2) Pin 16
Don't use Pin 16 (ZAP). It must be open.
3) Monitor function
a) Pin 21 of this IC has a function to monitor internal circuit terminals of this IC.
The monitor point of analog signal or digital signal is set by SUBADD : 04H, D0 to D3.
The choice of monitor point of logic signal is SUBADD : 0AH .It is chosen by D0 to D2 of 0AH.
b) Don't choose more than one monitor point (analog, logic) at the same time.
c) It is prohibited choosing the monitor point when IF limit amplifier is compulsory off (SUBADD : 04H, D7 = "0").
Be sure to turn on IF limit amplifier when you use monitor function.
d) Monitor function is a function for the test purpose only in our company, and its function is not guaranteed.
When it is needed to send data, all data must be "0". Don't use it with the actual tuner set.
4) Charge pump test function
a) SUBADD : 04H D4 to D5 are the bits for the function check of charge pump. For a normal use, they must be set to "0".
5) Handling unused bits
a) All unused bits must be set to "0". When it is necessary to input Subaddress data, all unused bits must be set to "0".
6) Set number of N divider
Don't establish N value about settlement of N divider in 271 or less.
7) The timing of IF counter
IF counter starts to count when it detects Stop condition of write mode at SDS mode (SUB ADD : 01H, D1 = "1").
The result of the IF count can get it when it begins to read it after the progress about more than 70 ms and it is made the
mode and begins to read it.
To prevent IF counter’s abnormal function, so that stop condition may not come between about 70 ms of the following.
(see the figure below.) Even if this timing isn't kept, IC doesn't become uncontrollable. But the following condition are
occurred by the transmitting data.
a) When there are data which turn off SDS :
Counter stops, and it is reset. The judgment result of IF counter isn't right. Ignore data and erase it.
b) In the case of the dummy data:
Stop condition is ignored, and IF counter works as it is. (It isn't reset.) If an original access prohibition time passes, the
proper result of IF counter is obtained.
Wait time
Gate time
reset
Start
(stop condition)
Access prohibition time : More than 70 ms. (Reference value)
SDC00079AEB
26
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