AOZ1036 Ver la hoja de datos (PDF) - Alpha and Omega Semiconductor
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AOZ1036 Datasheet PDF : 17 Pages
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AOZ1036
In a buck converter, output capacitor current is
continuous. The RMS current of output capacitor is
decided by the peak to peak inductor ripple current.
It can be calculated by:
ICO_RMS = --Δ----I--L--
12
Usually, the ripple current rating of the output capacitor
is a smaller issue because of the low current stress.
When the buck inductor is selected to be very small and
inductor ripple current is high, output capacitor could be
overstressed.
External Schottky Diode for High Input Operation
When VIN is higher than 16V, an external 1A schottky
diode is required between LX and PGND for proper
operation.
Loop Compensation
The AOZ1036 employs peak current mode control for
easy use and fast transient response. Peak current mode
control eliminates the double pole effect of the output
L&C filter. It greatly simplifies the compensation loop
design.
With peak current mode control, the buck power stage
can be simplified to be a one-pole and one-zero system
in frequency domain. The pole is dominant pole can be
calculated by:
fP1
=
----------------1------------------
2π × CO × RL
The zero is a ESR zero due to output capacitor and its
ESR. It is can be calculated by:
fZ1
=
-----------------------1-------------------------
2π × CO × ESRCO
where;
CO is the output filter capacitor,
RL is load resistor value, and
ESRCO is the equivalent series resistance of output capacitor.
The compensation design is actually to shape the
converter control loop transfer function to get desired
gain and phase. Several different types of compensation
network can be used for the AOZ1036. For most cases, a
series capacitor and resistor network connected to the
COMP pin sets the pole-zero and is adequate for a stable
high-bandwidth control loop.
In the AOZ1036, FB pin and COMP pin are the inverting
input and the output of internal error amplifier. A series
R and C compensation network connected to COMP
provides one pole and one zero. The pole is:
fP2
=
----------------G-----E----A-----------------
2π × CC × GVEA
where;
GEA is the error amplifier transconductance, which is
200 x 10-6 A/V,
GVEA is the error amplifier voltage gain, which is 500 V/V, and
CC is compensation capacitor in Figure 1.
The zero given by the external compensation network,
capacitor CC and resistor RC, is located at:
fZ2
=
-----------------1------------------
2π × CC × RC
To design the compensation circuit, a target crossover
frequency fC for close loop must be selected. The system
crossover frequency is where control loop has unity gain.
The crossover is the also called the converter bandwidth.
Generally a higher bandwidth means faster response to
load transient. However, the bandwidth should not be too
high because of system stability concern. When
designing the compensation loop, converter stability
under all line and load condition must be considered.
Usually, it is recommended to set the bandwidth to be
equal or less than 1/10 of switching frequency. The
AOZ1036 operates at a frequency range from 400kHz to
600kHz. It is recommended to choose a crossover
frequency equal or less than 40kHz.
fC = 40kHz
The strategy for choosing RC and CC is to set the
cross over frequency with Rc and set the compensator
zero with CC. Using selected crossover frequency, fC,
to calculate RC:
RC
=
fC
×
--V----O----
VFB
×
-----2----π----×-----C-----C------
GEA × GCS
where;
fC is desired crossover frequency. For best performance,
fC is set to be about 1/10 of switching frequency,
VFB is 0.8V,
GEA is the error amplifier transconductance, which is
200 x 10-6 A/V, and
GCS is the current sense circuit transconductance, which is
6.68 A/V.
Rev. 1.1 September 2010
www.aosmd.com
Page 10 of 17
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