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APL5320

Ultra-Low-Noise, High PSRR, Low-Dropout, 300mA Linear Regulator

Anpec Electronics 

APL5320

Application Information

Input capacitor

The APL5320 requires proper input capacitors to supply

surge current during stepping load transients to prevent

the input rail from dropping. Because the parasitic induc-

tor from the voltage sources or other bulk capacitors to

the VIN limit the slew rate of the surge current, place the

Input capacitors near VIN as close as possible. Input

capacitors should be larger than 1µF and a minimum

ceramic capacitor of 1µF is necessary.

Output Capacitor

The APL5320 needs a proper output capacitor to main-

tain circuit stability and improve transient response over-

temperature and current. In order to insure the circuit

stability, the proper output capacitor value should be larger

than 1µF. With X5R and X7R dielectrics, 1µF is sufficient

at all operating temperatures. Large output capacitor

value can reduce noise and improve load-transient re-

sponse and PSRR, Figure 1 shows the curves of allow-

able ESR range as the function of load current for various

output capacitor values.

Region of Stable COUT ESR vs. Output Current

10

APL5320-12

VCIINN==VCEONU=T4=.12µVF/X7R

1

Unstable Range

0.1

Stable Range

Operation Region and Power Dissipation

The APL5320 maximum power dissipation depends on

the thermal resistance and temperature difference be-

tween the die junction and ambient air. The TDFN1.6x1.6-6

package power dissipation P across the device is:

D

PD = (TJ - TA) / θJA

where (TJ - TA) is the temperature difference between the

junction and ambient air. θJA is the thermal resistance

between Junction and ambient air. Assuming the TA=25oC

and maximum TJ=160oC (typical thermal limit threshold),

the maximum power dissipation is calculated as:

PD(max)=(160-25)/165=0.81(W)

For normal operation, do not exceed the maximum junc-

tion temperature rating of T =125oC. The calculated power

J

dissipation should be less than:

PD=(125-25)/165=0.6(W)

The GND provides an electrical connection to the ground

and channels heat away. Connect the GND to the ground

by using a large pad or a ground plane.

Layout Consideration

Figure 2 illustrates the layout. Below is a checklist for

your layout:

1. Please place the input capacitors close to the VIN.

2. Ceramic capacitors for load must be placed near the

load as close as possible.

3. To place APL5320 and output capacitors near the load

is good for performance.

4. Large current paths, the bold lines in figure 2, must

have wide tracks.

0.01

Simulation Verify

VIN

VIN

SHDN VOUT

ON

GND

VOUT

0.001

0

OFF

50 100 150 200 250 300

Output Current (mA)

Figure2. Large Current Paths Shown as Bold Lines

Figure1. Stable COUT ESR Range

Copyright © ANPEC Electronics Corp.

12

Rev. A.9 - Mar., 2012

www.anpec.com.tw

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