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APW7078

Single PWM Switching Controller

Anpec Electronics 

APW7078

Function Description (Cont.)

Setting Output Voltage (Cont.)

VOUT

=

1



+

R3

R2





×

0.5V

To avoid the thermal nois e from feedback resistor,

Resistance R2 smaller than 100kΩ and 1% variation

is recommended.

Error amplifier

The error amplifier detects the output voltage of the

swit ching regulat or and out put s the PW M control

signal. The voltage gain is fixed, and connec ting a

phase compensation resistor and capacitor to the FB

pin (pin 8) provides stable phase compensation for the

system.

PWM comparator

The volt age c omparator has one invert ing and three

non-inverting inputs. The comparator is a voltage/pulse

width converter that controls the ON time of the output

pulse depending on the input voltage. The output level

is high (H) when the sawtooth wave is lower than the

error amplifier output voltage, soft start setting voltage,

and idle period setting voltage.

Output circuit

The output circuit is a typical push-pull configuration

to drive an external NMOS transistor directly. It can

provide a 200mA source/sink to/from OUT(pin 6).

Soft start and short circuit detection

Soft start operation is set by connecting capacitor Cscp

to t he SCP pin (pin 2). Soft s tart prevents a current

spike on start-up.On completion of soft start operation,

the SCP pin (pin 2) s tays low and enters the short

circuit detection wait stat e.When an output short cir-

cuit occurs, the error amplifier output is fixed at 1.8V

and capacitor Cscp starts charging.

After charging to approximately 0.8 V, t he output pin

(pin 5) is set low and the SCP pin stays low. Once the

protection circuit operates, the circuit can be restored

by resetting the power supply. Short circuit detection

time can be calculate as follow:

t SCP = 0.8 × Cscp(µ F)

Under Voltage Lock Out(UVLO)

Trans ient s during powering on or inst ant aneous

glitches in the supply voltage can cause system dam-

age or failure. The circuit to prevent malfunction at low

input voltage detect s a low input voltage by compar-

ing the supply voltage to the internal reference voltage.

On detection, the circuit fixes the output pin to low.

The system recovers when the supply voltage rises

back above the t hreshold volt age of the malfunc tion

prevention circuit.

Layout Considerations

Switching Noise Decoupling Capacitor

A 0.1µF ceramic capacitor should be placed close to

the V OUT pin and GND pin of the chip t o filter t he

switc hing spikes in t he output voltage monitored by

the VOUT pin.

Feedback Network

On A PW7078 applicat ion, the feedback networks

should be connec ted directly to a dedicated analog

ground plane and this ground plane must connect to

the GND pin. If no analog ground plane is available

then this ground must tie directly to the GND pin. The

feedback network, resistors R2 and R3, should be kept

close to the FB pin, and away from the inductor, to

minimize copper trace connections that can inject noise

into the system.

Input Capacitor

The input capacitor CIN in VIN must be placed close to

the IC. This will reduce copper trace resistance which

C opyright © ANPEC Electronics C orp.

10

Rev. A.3 - Nov., 2005

www.anpec.com.tw

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