AS7C33128PFD32A Ver la hoja de datos (PDF) - Alliance Semiconductor

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AS7C33128PFD32A

3.3V 128K × 32/36 pipeline burst synchronous SRAM

Alliance Semiconductor 

®

Timing waveform of write cycle

tCYC

tCH

tCL

CLK

ADSP

tADSPS

tADSPH

AS7C33128PFD32A

AS7C33128PFD36A

ADSC

Address

tAS

tAH

A1

A2

BWE

BW[a:d]

tADSCS

tADSCH

ADSC LOADS NEW ADDRESS

A3

tWS

tWH

CE0, CE2

tCSS

tCSH

CE1

ADV SUSPENDS BURST

tADVS

tADVH

ADV

OE

Data In

D(A1)

D(A2) D(A2Ý01) D(A2Ý01) D(A2Ý10) D(A2Ý11) D(A3)

tDS

tDH

D(A3Ý01) D(A3Ý10)

Note: Ý = XOR when MODE = HIGH/No Connect; Ý = ADD when MODE = LOW.

3/22/01; v.1.0

Alliance Semiconductor

P. 8 of 11

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