AS7C33256PFS32A Ver la hoja de datos (PDF) - Alliance Semiconductor

Número de pieza

componentes Descripción

Lista de partido

AS7C33256PFS32A

3.3V 256K × 32/36 pipelined burst synchronous SRAM

Alliance Semiconductor 

AS7C33256PFS32A

AS7C33256PFS36A

®

Signal descriptions

Signal

I/O

CLK

I

A, A0, A1 I

DQ[a,b,c,d] I/O

CE0

I

CE1, CE2 I

ADSP

I

ADSC

I

ADV

I

GWE

I

BWE

I

BW[a,b,c,d] I

OE

I

LBO

I

ZZ

I

NC

-

Properties

CLOCK

SYNC

SYNC

SYNC

SYNC

SYNC

SYNC

SYNC

SYNC

SYNC

SYNC

ASYNC

STATIC

ASYNC

-

Description

Clock. All inputs except OE, ZZ, LBO are synchronous to this clock.

Address. Sampled when all chip enables are active and ADSC or ADSP are asserted.

Data. Driven as output when the chip is enabled and OE is active.

Master chip enable. Sampled on clock edges when ADSP or ADSC is active. When CE0

is inactive, ADSP is blocked. Refer to the Synchronous Truth Table for more

information.

Synchronous chip enables. Active HIGH and active LOW, respectively. Sampled on

clock edges when ADSC is active or when CE0 and ADSP are active.

Address strobe processor. Asserted LOW to load a new bus address or to enter standby

mode.

Address strobe controller. Asserted LOW to load a new address or to enter standby

mode.

Advance. Asserted LOW to continue burst read/write.

Global write enable. Asserted LOW to write all 32/36 bits. When HIGH, BWE and

BW[a:d] control write enable.

Byte write enable. Asserted LOW with GWE = HIGH to enable effect of BW[a:d]

inputs.

Write enables. Used to control write of individual bytes when GWE = HIGH and BWE =

LOW. If any of BW[a:d] is active with GWE = HIGH and BWE = LOW the cycle is a

write cycle. If all BW[a:d] are inactive the cycle is a read cycle.

Asynchronous output enable. I/O pins are driven when OE is active and the chip is in

read mode.

Selects Burst mode. When tied to VDD or left floating, device follows Interleaved Burst

order. When driven Low, device follows linear Burst order. This signal is internally

pulled High.

Snooze. Places device in LOW power mode; data is retained. Connect to GND if unused.

No connect

Snooze Mode

SNOOZE MODE is a low current, power-down mode in which the device is deselected and current is reduced to ISB2. The duration of

SNOOZE MODE is dictated by the length of time the ZZ is in a High state.

The ZZ pin is an asynchronous, active high input that causes the device to enter SNOOZE MODE.

When the ZZ pin becomes a logic High, ISB2 is guaranteed after the time tZZI is met. After entering SNOOZE MODE, all inputs except ZZ

is disabled and all outputs go to High-Z. Any operation pending when entering SNOOZE MODE is not guaranteed to successfully complete.

Therefore, SNOOZE MODE (READ or WRITE) must not be initiated until valid pending operations are completed. Similarly, when exiting

SNOOZE MODE during tPUS, only a DESELECT or READ cycle should be given while the SRAM is transitioning out of SNOOZE MODE.

11/30/04, v.3.1

Alliance Semiconductor

P. 5 of 20

Share Link: