AS8202NF-ALQT Ver la hoja de datos (PDF) - austriamicrosystems AG
Número de pieza
componentes Descripción
Lista de partido
AS8202NF-ALQT Datasheet PDF : 20 Pages
| |||
AS8202NF TTP-C2NF
Data Sheet - Pin Assignments
Table 1. Pin Descriptions
Pin Name Pin Number
Dir
Description
XIN0
2
A
Main Clock: Analog CMOS Oscillator Input, use as input when
providing external clock
XOUT0
3
A
Main Clock: Analog CMOS Oscillator Output, leave open when
providing external clock
PLLOFF
23
IPD
Main Clock PLL Disable Pin, connect to VSS when providing 10 MHz
crystal for enabling the internal PLL
XIN1
72
A
Bus Guardian Clock: Analog CMOS Oscillator Input, use as input
when providing external clock
XOUT1
71
A
Bus Guardian Clock: Analog CMOS Oscillator Output, leave open
when providing external clock
RESETB
26
IPU
Main Reset Input, active low
TxD0
5
OPU
TTP Bus Channel 0: Transmit Data
CTS0
6
OPD
TTP Bus Channel 0: Transmit Enable
RxD0
11
IPU
TTP Bus Channel 0: Receive Data
TxCLK0
7
IPD
TTP Bus Channel 0: Transmit Clock (MII mode)
RxER0
8
IPU
TTP Bus Channel 0: Receive Error (MII mode)
RxCLK0
9
IPD
TTP Bus Channel 0: Receive Clock (MII mode)
RxDV0
10
IPU
TTP Bus Channel 0: Receive Data Valid (MII mode)
TxD1
14
OPU
TTP Bus Channel 1: Transmit Data
CTS1
15
OPD
TTP Bus Channel 1: Transmit Enable
RxD1
20
IPU
TTP Bus Channel 1: Receive Data
TxCLK1
16
IPD
TTP Bus Channel 1: Transmit Clock (MII mode)
RXER1
17
IPU
TTP Bus Channel 1: Receive Error (MII mode)
RXCLK1
18
IPD
TTP Bus Channel 1: Receive Clock (MII mode)
RxDV1
19
IPU
TTP Bus Channel 1: Receive Data Valid (MII mode)
A[11:0]
48-42, 39-35
I
Host Interface (CNI) Address Bus1
D[15:0] 69-62, 58-51
I/O
Host Interface (CNI) Data Bus, tristate
CEB
76
IPU
Host Interface (CNI) Chip Enable, active low
OEB
77
IPU
Host interface (CNI) output enable, active low
WEB
78
IPU
Host interface (CNI) write enable, active low
READYB
79
OPU
Host interface (CNI) transfer finish signal, active low, open drain2
INTB
28
OPU
Host interface (CNI) time signal (interrupt), active low, open drain
LED[2:0]
33-31
OPD
Configurable generic output port
nc
1, 27, 40
Not connected, leave open
1. The device is addressed at 16-bit data word boundaries. If the device is connected to a CPU with a byte-
granular address bus, remember that A[11:0] of the AS8202NF device has to be connected to A[12:1] of the
CPU (considering a little endian CPU address bus)
2. At de-assertion READYB is driven to the inactive value (high) for a configurable time.
Table 2. Pin Directions
Dir
I
IPU
IPD
I/O
OPU
Description
TTL Input
TTL Input with Internal Weak Pull-Up
TTL Input with Internal Weak Pull-Down
TTL Input/Output with Tristate
TTL Output with Internal Weak Pull-Up at Tristate
www.austriamicrosystems.com and
TTTech Computertechnik AG
Revision 2.1
4 - 20
Share Link: 