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PDI1394P11 Datasheet PDF : 20 Pages
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Philips Semiconductors
3-port physical layer interface
Product specification
PDI1394P11
18.0 EXTERNAL COMPONENTS AND CONNECTIONS
18.1 Logic Reset input (RESET–, pin 1)
Forcing this pin low causes a Bus Reset condition on the active
cable ports, and resets the internal logic to the Reset Start state.
SYSCLK remains active. An internal pull-up resistor is provided that
is connected to VDD, so only an external delay capacitor is required.
This input is a standard logic buffer and may also be driven by an
open drain logic output buffer. The RESET pin also has a n-channel
pull-down transistor activated by the PD (Power Down) pin.
18.2 Link Power Status input (LPS, pin 2)
In a non-isolated implementation a 10kΩ resistor is connected to the
VDD supplying the link layer controller to monitor the link’s power
status. In an isolated implementation a square wave with a minimum
frequency of 500 kHz can be applied to the LPS pin to indicate the
pin is powered. If the link is not powered on the Control I/O’s (pins
11,12), Data I/O’s (pins 13 – 16) and SYSCLK output (pin 9) are
disabled, and the PDI1394P11 will perform only the basic repeater
functions required for network initialization and operation.
18.3 Link Request input (LREQ, pin 3)
LREQ is a signal from the link layer controller used to request the
PDI1394P11 to perform some service. This pin supports an optional
isolation barrier.
18.4 Power Down input (PD, pin 7)
This input powers down all device functions with the exception of the
CNA circuit to conserve power in portable or battery powered
applications. It must be held high for at least 3.5ms to assure a
successful reset after power down. This pin supports an optional
isolation barrier.
18.5 System Clock output (SYSCLK, pin 9)
Provides a 49.152 MHz clock signal, synchronized with the data
transfers, to the link layer controller. This pin supports an optional
isolation barrier.
18.6 Control I/Os (CTL[0:1], pins[11,12])
These are bi-directional signals used in the communication between
the PDI1394P11 and the link layer controller that control passage of
information between the two devices. These pins support an
optional isolation barrier.
18.7 Data I/Os (D[0:3], pins [13,14,15,16])
These are bi-directional information signals used in the
communication between the PDI1394P11 and the link layer
controller. These pins support an optional isolation barrier.
18.8 Test Mode control and ISBR mode inputs
(TESTM[1:2], pins[22,21])
These two logic signals are used in manufacturing to enable
production line testing of the PDI1394P11. For normal use these
should be tied to VDD. To enable ISBR (Arbitrated (short) bus reset)
mode, set TESTM1 high and TESTM2 low. See section 17.1 for
more information on ISBR mode.
18.9 Cable Power Status input (CPS, pin 23)
This is normally connected to the cable power through an external
resistor. The circuit drives an internal comparator which is used to
detect the presence of cable power. This information is maintained
in an internal register and is available to the link layer controller
through a register read. See section 17.2 for information on setting
the CPS trip point.
18.10 Bus or Isochronous Resource Manager
Capable input or Link-On output (C/LKON, pin 27)
This is a bi-directional pin that is used as an input to specify, in the
Self-ID packet, that the node is Bus or Isochronous Resource
Manager Capable. As an output it signals the reception of a Link-On
message by supplying a 6.114 MHz signal. The bit value
programming is done by tying the pin through a 10kΩ resistor to a
high (VDD) or low (GND). The use of the series resistor allows the
Link-On to override the input value when necessary.
18.11 Power Class bits 0 through 2 inputs
(PC[0:2], pins [30,29,28])
Used as inputs to set the bit values of the three Power Class bits in
the self-ID packet (bits 21, 22 and 23). These bits can be
programmed by tying the pins high to VDD or low to GND.
18.12 Cable Not Active output (CNA, pin 31)
This pin outputs the cable connection status. If all ports are
disconnected this pin outputs a high. If any port has a cable
connected then this pin outputs a low.
18.13 Twisted Pair I/O’s (TPA[1:3]+,
pins [45, 40, 36], TPA[1:3]–, pins [44,39,35],
TPB[1:3]+, pins [43,38,34], TPB[1:3]–,
pins [42, 37, 33])
These pins send and receive differential data over the twisted pair
cables. Two series connected external 56 Ω cable termination
resistors are required at each twisted pair. Each unused TPB pin
must be tied through a 5kΩ resistor to ground. The TPA pins can be
left floating.
18.14 Twisted Pair Bias outputs (TPBIAS[1:3],
pins [46, 47, 48])
These outputs provide the 1.86 V nominal bias voltage needed for
proper operation of the twisted pair cable drivers, and for signaling
to the remote nodes that there is a valid cable connection. Three
TPBIAS outputs are provided for separate connection to each of the
three TPA twisted pairs to provide electrical isolation. A 1µF
capacitor to ground must be connected to each TPBIAS pin whether
it is used or not.
18.15 PLL Filter (FILTER, pin 54)
This pin is connected to an external filter capacitor used in a
lag-lead filter for a PLL frequency multiplier running off of the crystal
oscillator.
18.16 Oscillator crystal (Xl, pin 56 & XO, pin 57)
These pins connect to a 24.576 MHz parallel resonant fundamental
mode crystal. The optimum values for the external shunt capacitors
are dependent on the specifications of the crystal used, the
suggested values of 12 pF are appropriate for one specified for
15 pF loads.
18.17 Current setting resistor (R[0:1],
pins [59,60])
An internal reference voltage is applied across the resistor
connected between these two pins to set the internal operating and
the cable driver output currents. A low TCR (<150ppm/°C
temperature coefficient) with a value of 6.34 kΩ ±1% should be used
to meet the 1394 standard output voltage limits.
1999 Apr 09
12
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