BD9206EFV Ver la hoja de datos (PDF) - ROHM Semiconductor
Número de pieza
componentes Descripción
Lista de partido
BD9206EFV Datasheet PDF : 13 Pages
| |||
BD9206EFV
Technical Note
●Notes for use
1.) The absolute maximum ratings
We pay sufficient attention for quality control to this product but If the absolute maximum ratings are exceeded, such as with
applied voltage or operational temperature range, a degradation or a destruction may occur. The short or open modes cannot be
specified. so if special modes which exceed the absolute maximum ratings are assumed, physical safety precautions such as fuses
should be in place.
2.) Reverse connection of power supply connector
The reverse connection of power connector may cause damage to IC. Please take countermeasures such as inserting a
diode between the power supply and IC’s external power supply pin for protection against the damage caused by the
reverse connection.
3.) Power supply line
The return of the regenerated current is caused by the back electromotive force of the external coil, so please take the
measures such as inserting a capacitor between power supply and GND as a route of regenerated current, and determine
the capacitance value after thoroughly ensuring that there is no problems in the Characteristics of electrolyte capacitor,
such as no loss of capacitance at low temperature. Heat design should take into account of power dissipation (Pd) under actual
usage conditions, with wide enough margins
4.) GND Potential
The potential of the GND terminal should be the minimum potential under all operating conditions.
5.) Heat Design
Heat design should take into account of power dissipation under actual usage conditions, with wide enough margins.
6.) Short-circuiting between Terminals and Incorrect Mounting
When mounting to the PWB, pay special attention to the direction and proper placement of the IC. If the IC is attached incorrectly,
it may be destroyed. Furthermore, there is also a possibility of breakdown, when the foreign body enters during outputting and
between power supply and GND.
7.) The operation in the strong magnetic fields
Please be careful that there is a possibility of malfunction which is happening when you use it in a strong electromagnetic
field.
8.) ASO
Please do the setting in such a way that the output Tr does not exceed the absolute maximum rating and ASO in case of
using this IC. For CMOS IC and the IC with more than one power supply, a rush current may flow instantaneously at the
time of power on, so please be careful about power supply coupling capacitance, power supply, GND pattern wiring width
and length.
9.) Thermal shutdown circuit (TSD circuit)
This IC incorporates a built-in thermal shutdown circuit (TSD circuit). The TSD circuit is that has designed only to shut the
IC off to prevent the thermal runaway operation，not for IC protection or guarantee as purpose. Therefore, please do not
continue to use the IC after operating this circuit and also do not use the IC designating operation as prerequisite.
10.) Inspection of the Set Substrate
If a condenser is connected to a pin with low impedance when inspecting the set substrate, stress may be placed on the IC,
so please be sure to discharge after each process. Moreover, please be sure to turn off the power supply before connecting
& inspecting or before detaching when it is connected to jig at inspection process.
11.) About IC terminal input
This IC is a monolithic IC, and there are a P+ isolation and the P substrate for separation of element between each element. There is
a P-N junction formed between this P-layer and each element’s N-layer, forming every parasitic element, as shown in Fig.15, when
resistance and transistor are connected with terminal
〇 In the case of GND>（terminal A ）with resistance or GND>(terminal B) with transistor(NPN), the P-N junction operates as a
parasitic diode.
〇 In addition, when GND> (terminal B) with the transistor (NPN), the parasitic NPN transistor operates due to the aforementioned
parasitic diode and the N layer of the other element approached
With the IC’s configuration, the production of parasitic elements is inevitable. The operation of parasitic elements causes
interferences between circuits, leading to malfunction and even destruction. Therefore, uses which cause the parasitic elements
to operate, such as applying voltage to the input terminal which is lower than the GND (P-substrate), should be avoided.
(terminalA)
(端子A)
R抵e抗sistance
Transistor
トランジスタ
(te(r端mi子naBlB) )
B
C (NPN)
E
P＋
N
P
N
P＋
N
PPS基ubs板trate P寄ar生as素itic子Element
GND
P＋
Ｎ
N
P
N
P Substrate
P 基板
Parasitic寄E生lem素e子nt
GND
GND
P＋
N
(terminalA)
(端子A)
Para寄sit生ic 素Ele子ment
(terminalB)
(端子B)
BC
E
GND
GND
other e近lem接enすt aるpp他roaのche素d 子
P寄ar生asi素tic子Element
Fig.11FigS..i1m1pバleイSポtruーctラureICoのf b簡ip易ola構r 造IC例(Sample)
www.rohm.com
© 2009 ROHM Co., Ltd. All rights reserved.
11/12
2009.07 - Rev.A
Share Link: 