BS616LV1015AI Ver la hoja de datos (PDF) - Brilliance Semiconductor
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BS616LV1015AI Datasheet PDF : 9 Pages
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BSI
LOW VCC DATA RETENTION WAVEFORM ( CE Controlled )
Vcc
CE
Vcc
t CDR
VIH
Data Retention Mode
VDR ≥ 1.5V
CE ≥ Vcc - 0.2V
BS616LV1015
Vcc
tR
VIH
AC TEST CONDITIONS
Input Pulse Levels
Vcc/0V
Input Rise and Fall Times 1V/ns
Input and Output
Timing Reference Level
Output Load
0.5Vcc
CL=30pF+1TTL
CL=100pF+1TTL
KEY TO SWITCHING WAVEFORMS
WAVEFORM
INPUTS
MUST BE
STEADY
MAY CHANGE
FROM H TO L
MAY CHANGE
FROM L TO H
,
DON T CARE:
ANY CHANGE
PERMITTED
DOES NOT
APPLY
OUTPUTS
MUST BE
STEADY
WILL BE
CHANGE
FROM H TO L
WILL BE
CHANGE
FROM L TO H
CHANGE :
STATE
UNKNOWN
CENTER
LINE IS HIGH
IMPEDANCE
”OFF ”STATE
AC ELECTRICAL CHARACTERISTICS ( TA = 0oC to + 70oC, Vcc = 5.0V )
READ CYCLE
JEDEC
PARAMETER
NAME
t
AVAX
t
AVQV
t
E1LQV
t
BA
t
GLQV
t
E1LQX
t
BE
t
GLQX
t
E1HQZ
t
BDO
t
GHQZ
t
AXOX
PARAMETER
NAME
t
RC
t
AA
t
ACS
t
BA
t
OE
t
CLZ
t
BE
t
OLZ
t
CHZ
t
BDO
t
OHZ
t
OH
DESCRIPTION
Read Cycle Time
Address Access Time
Chip Select Access Time
Data Byte Control Access Time
Output Enable to Output Valid
Chip Select to Output Low Z
Data Byte Control to Output Low Z
Output Enable to Output in Low Z
Chip Deselect to Output in High Z
Data Byte Control to Output High Z
Output Disable to Output in High Z
Data Hold from Address Change
(CE)
(LB,UB)
(CE)
(LB,UB)
(CE)
(LB,UB)
CYCLE TIME : 55ns
MIN. TYP. MAX.
55
--
--
--
--
55
--
--
55
--
--
35
--
--
35
10
--
--
10
--
--
10
--
--
--
--
35
--
--
35
--
--
30
5
--
--
UNIT
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
R0201-BS616LV1015
4
Revision 1.1
Jan. 2004
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