BS616LV2019(2006) Ver la hoja de datos (PDF) - Brilliance Semiconductor

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BS616LV2019
(Rev.:2006)

Very Low Power CMOS SRAM 128K X 16 bit

Brilliance Semiconductor 

READ CYCLE 2 (1,3,4)

CE

CE2

DOUT

READ CYCLE 3 (1, 4)

ADDRESS

OE

CE

CE2

LB, UB

DOUT

tACS1

tACS2(6)

tCLZ(5,6)

tRC

tAA

tOE

tOLZ

tACS1

t (6)

ACS2

tCLZ(5,6)

tBA

tBE

BS616LV2019

tCHZ(5, 6)

tOH

tOHZ(5)

tCHZ(1,5,6)

tBDO

NOTES:

1. WE is high in read Cycle.

2. Device is continuously selected when CE = VIL and CE2= VIH.

3. Address valid prior to or coincident with CE transition low and/or CE2 transition high.

4. OE = VIL.

5. Transition is measured ± 500mV from steady state with CL = 5pF.

The parameter is guaranteed but not 100% tested.

6. 48B BGA ignore this parameters related to CE2.

R0201-BS616LV2019

6

Revision 1.3

May.

2006

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