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BT861KRF

Multiport YCrCb to NTSC / PAL / SECAM Digital Video Encoder

Conexant Systems 

1.0 Functional Description

1.1 Pin Descriptions

Table 1-1. Pin Assignments (1 of 3)

Pin Name I/O

Pin #

P[7:0]

I 22-19, 16-13

CLKO

VSYNC*

O 70

I/O 24

HSYNC*

I/O 25

BLANK*

I 23

FIELD

O 26

VID[7:0]

I 6-1, 80-79

VIDCLK

VIDHACT

I9

I 12

VIDVACT

VIDFIELD

I 11

I 72

VIDVALID

I

10

Bt860/861

Multiport YCrCb to NTSC/PAL /SECAM

Description

PRIMARY VIDEO PORT

Primary video input port (TTL compatible)(1). Accepts pixel data in 8-bit YCrCb 4:2:2

format in either ITU-R BT.601 or ITU-R BT.656 control formats. A higher index

corresponds to a greater bit significance. By default, data is latched on the rising

edge of the system clock(2).

2x pixel clock output. The clock generated by the PLL is produced at this pin when

register bit CLKO_DIS = 0.

Vertical sync input/output (TTL compatible). As an output (master mode operation),

VSYNC* follows the rising edge of the system clock. As an input (slave mode

operation), VSYNC* is, by default, registered on the rising edge of the system

clock(2). The VSYNCI register bit controls the polarity of this signal.

Horizontal sync input/output (TTL compatible). As an output (master mode

operation), HSYNC* follows the rising edge of the system clock. As an input (slave

mode operation), HSYNC* is, by default, registered on the rising edge of the system

clock(2). The HSYNCI register bit controls the polarity of this signal.

Composite blanking control input (TTL compatible). By default, BLANK* is

registered on the rising edge of the system clock(2). The video data inputs are

ignored while BLANK* is a logical 0. The BLANKI register bit controls the polarity of

this signal.

Field control output (TTL compatible). FIELD transitions after the rising edge of the

system clock, two clock cycles following a falling HSYNC*. The FIELDI register bit

controls the polarity of this signal. The state of this pin at power-up determines the

default state of the PCLK_SEL register bit and the initial clock source. If not

externally loaded, this pin will be pulled low with an internal pull-down resistor.

SECONDARY VIDEO PORT

Secondary video input port (TTL compatible). Accepts pixel data in 8-bit YCrCb

4:2:2 format. A higher index corresponds to a greater bit significance. By default,

data on the VID port is latched by the rising edge of VIDCLK(1) (3).

Pixel clock for secondary video input port(1).

Horizontal active display region. A logical 1 indicates data on VID[7:0] is in the

horizontal display region. The VIDHACTI register bit controls the polarity of this

signal. By default, data on VIDHACT is latched by the rising edge of VIDCLK(1) (3).

Vertical active display region. The VIDVACTI register bit controls the polarity of this

signal. By default, data on VIDVACT is latched by the rising edge of VIDCLK(1) (3).

Field indicator for video input port. A logical 1 indicates data is from an even field.

The VIDFIELDI register bit controls the polarity of this signal. By default, data on

VIDFIELD is latched by the rising edge of VIDCLK(1) (3).

Video data valid qualifier. A logical 1 indicates data on VID[7:0] is valid data. The

VIDVALIDI register bit controls the polarity of this signal. By default, data on

VIDVALID is latched by the rising edge of VIDCLK(1) (3).

1-2

Conexant

D860DSA

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