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PI74ALVCH16821 Ver la hoja de datos (PDF) - Pericom Semiconductor

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PI74ALVCH16821 Datasheet PDF : 5 Pages
1 2 3 4 5
PI74ALVCH16821
1122334455667788990011223344556677889900112233445566778899001122112233445566778899001122334455667788990011223344556677889900112211223344556677889900112233445566778899001122334455667788990011221122334455667788990011223344556677889900112233445566778899001122112233445566778899001122
3.3V 20-Bit Bus Interface Flip-Flop
with 3-State Outputs
Product Features
PI74ALVCH16821 is designed for low voltage operation
VCC = 2.3V to 3.6V
Hysteresis on all inputs
Typical VOLP (Output Ground Bounce)
< 0.8V at VCC = 3.3V, TA = 25°C
Typical VOHV (Output VOH Undershoot)
< 2.0V at VCC = 3.3V, TA = 25°C
Bus Hold retains last active bus state during 3-STATE,
eliminating the need for external pullup resistors
Industrial operation at –40°C to +85°C
Packages available:
– 56-pin 240 mil wide plastic TSSOP (A)
– 56-pin 300 mil wide plastic SSOP (V)
Logic Block Diagram
Description
Pericom Semiconductor’s PI74ALVCH series of logic circuits are
produced in the Company’s advanced 0.5 micron CMOS
technology, achieving industry leading speed.
The PI74ALVCH16821 is a 20-bit bus interface flip-flop designed
for 2.3V to 3.3V VCC operation. It can be used as two 10-bit flip-
flops or one 20-bit flip-flops. The 20 flip-flops are edge-triggered
D-type flip-flops. On the positive transition of the clock (CLK)
input, the device provides true data at the Q outputs.
A buffered output-enable (OE) input can be used to place the ten
outputs in either a normal logic state (HIGH or LOW level) or a
high-impedance state. In the high-impedance state, the outputs
neither load nor drive the bus lines significantly. The high-
impedance state and increased drive provide the capacity to drive
bus lines without the need for interface or pullup components.
OE does not affect the internal operation of the flip-flops. Old data
can be retained or new data can be entered while the outputs are in
the high-impedance state.
To ensure the high-impedance state during power up or power
down, OE should be tied to VCC through a pullup resistor; the
minimum value of the resistor is determined by the current sinking
capability of the driver.
Active bus-hold circuitry is provided to hold unused or floating
data inputs at a valid logic level.
1
1OE
1CLK 56
1D1 55
One of Ten
Channels
C1
1D
2OE 28
2CLK 29
2
1Q1
2D1 42
One of Ten
Channels
C1
1D
15
2Q1
TO 9 OTHER CHANNELS
TO 9 OTHER CHANNELS
1
PS8156 11/17/97

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