PI6C39911-2J Ver la hoja de datos (PDF) - Pericom Semiconductor Corporation
Número de pieza
componentes Descripción
Lista de partido
PI6C39911-2J
Pericom Semiconductor Corporation
PI6C39911-2J Datasheet PDF : 11 Pages
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PI6C39911/PI6C39912
3.3V High Speed LVTTL or Balanced Output
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Operational Mode Descriptions
REF
System Clock
FB
REF
FS
4F0
4Q0
4F1
4Q1
3F0
3Q0
3F1
3Q1
2F0
2Q0
2F1
2Q1
1F0
1Q0
1F1
1Q1
TEST
L1
Z0
L2
Z0
L3
Z0
L4
Z0
LOAD
LOAD
LOAD
LOAD
LENGTH: L1 = L2 = L3 = L4
Figure 2. Zero-Skew and/or Zero-Delay Clock Driver
Figure 2 shows the SUPERCLOCK configured as a zero-skew clock
buffer. In this mode the PI6C39911 can be used as the basis for a low-
skew clock distribution tree. When all of the function select inputs
(xF0, xF1) are left open, the outputs are aligned and may each drive
a terminated transmission line to an independent load. The FB input
can be tied to any output in this configuration and the operating
frequency range is selected with the FS pin. The low-skew specifi-
cation, coupled with the ability to drive terminated transmission lines
(with impedances as low as 50 ohms), allows efficient printed circuit
board design.
REF
System Clock
FB
REF
FS
4F0
4Q0
4F1
4Q1
3F0
3Q0
3F1
3Q1
2F0
2Q0
2F1
2Q1
1F0
1Q0
1F1
1Q1
TEST
L1
Z0
L2
Z0
L3
Z0
L4
Z0
LOAD
LOAD
LOAD
LOAD
LENGTH: L1 = L2, L3 < L2 by 6", L4 > L2 by 6"
Figure 3. Programmable Skew Clock Driver
7
PS8497A 04/10/01
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