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PI6C39912-2J

3.3V High Speed LVTTL or Balanced Output Programmable Skew Clock Buffer-SuperClock®

Pericom Semiconductor Corporation 

PI6C39911/PI6C39912

3.3V High Speed LVTTL or Balanced Output

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20 MHz

FB

REF

FS

4F0

4F1

3F0

3F1

2F0

2F1

1F0

1F1

TEST

REF

4Q0

4Q1

3Q0

3Q1

2Q0

2Q1

1Q0

1Q1

10 MHz

5 MHz

20 MHz

Figure 6. Frequency Divider Connections

Figure 6 demonstrates the SuperClock in a clock divider application.

2Q0 is fed back to the FB input and programmed for zero skew. 3Qx

is programmed to divide by four. 4Qx is programmed to divide by two.

Note that the falling edges of the 4Qx and 3Qx outputs are aligned.

This allows use of the rising edges of the ½ frequency and ¼

frequency without concern for skew mismatch. The 1Qx outputs are

programmed to zero skew and are aligned with the 2Qx outputs. In

this example, the FS input is grounded to configure the device in the

15 to 30 MHz range since the highest frequency output is running

at 20 MHz.

Figure 7 shows some of the functions that are selectable on the 3Qx

and 4Qx outputs. These include inverted outputs and outputs that

offer divide-by-2 and divide-by-4 timing. An inverted output allows

the system designer to clock different sub-systems on opposite

edges, without suffering from the pulse asymmetry typical of non-

ideal loading. This function allows the two subsystems to each be

clocked 180 degrees out of phase, but still to be aligned within the

skew specification.

The divided outputs offer a zero-delay divider for portions of the

system that need the clock to be divided by either two or four, and

still remain within a narrow skew of the “1X” clock. Without this

feature, an external divider would need to be add-ed, and the

propagation delay of the divider would add to the skew between the

different clock signals.

These divided outputs, coupled with the Phase Locked Loop, allow

the SuperClock to multiply the clock rate at the REF input by either

two or four. This mode will enable the designer to distribute a low-

frequency clock between various portions of the system, and then

locally multiply the clock rate to a more suitable frequency, while still

maintaining the low-skew characteristics of the clock driver. The

SuperClock can perform all of the functions described above at the

same time. It can multiply by two and four or divide by two (and four)

at the same time that it is shifting its outputs over a wide range or

maintaining zero skew between selected outputs.

27.5 MHz

Distribution

Clock

FB

REF

FS

4F0

4F1

3F0

3F1

2F0

2F1

1F0

1F1

TEST

REF

4Q0

4Q1

3Q0

3Q1

2Q0

2Q1

1Q0

1Q1

Z0

110 MHz

Inverted

27.5 MHz Z0

LOAD

LOAD

110 MHz

Zero Skew Z0

LOAD

110 MHz Skewed

–2.273ns (–4tU) Z0

LOAD

Figure 7. Multi-Function Clock Driver

9

PS8497A 04/10/01

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