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NWK933

3.3V 10/100 Fast Ethernet Transceiver to MII

Mitel Networks 

NWK933

TX_EN TX_ER

TXD [3:0]

Indication

0

X

ignored

Normal inter frame data

1

0 0000 through 1111 Normal data transmission

1

1 0000 through 1111 Transmit error propagation

Figure 3. 100Mb/s Transmit Error States

100Mb/s Receive Errors

When there is no data on the cable, the receiver will

see only the idle code of scrambled 1’s. If a non idle

symbol is detected, the receiver looks for the SSD so

that it can align the incoming message for decoding.

If any 2 non consecutive zeros are detected within 10

bits, but are not the SSD symbols a false carrier

indication is signalled to the MII by asserting RX_ER

and setting RXD[3:0] to 1110 whilst keeping RX_DV

inactive. The remainder of the message is ignored

until 10 bits of 1’s are detected.

If any data is decoded after a SSD which is neither a

valid data code nor an ESD, then an error is flagged

by setting RX_ER active whilst the RX_DV signal is

active. This also happens if 2 idle codes are detected

before a valid ESD has been received or descramble

synchronisation is lost during packet reception. The

states of RX_DV and RX_ER are summarised in

Figure 4. RX_ER is clocked on the falling edge of

RX_CLK, and will remain active for at least 1 period

of RX_CLK.

RX_DV RX_ER

RXD [3:0]

Indication

0

0 0000 through 1111 Normal inter frame

0

1

1110

False carrier indication

1

0 0000 through 1111 Normal data reception

1

1

0101 or 0110 Data reception with errors

Figure 4. 100Mb/s receive error states

CONTROLS

Initialization, mode selection and other options are

governed by the control inputs and register as

described in the following paragraphs.

Initialization (RESET_N)

The NWK933 incorporates a power-on-reset circuit

for self-initialization on power-up. During initialization

the open-drain RESET_N pin is driven low and all

data outputs are disabled to prevent spurious outputs

to the twisted-pair and to the MII interface. RESET_N

will remain low until the power supply has been stable

for at least 400ns. The NWK933 will then release

RESET_N allowing the external pull-up to pull the pin

high. Device initialisation will not commence until

RESET_N is high. This allows the user to extend the

inactive period by externally holding RESET_N low.

It will not normally be necessary for the user to reset

the NWK933 because it is designed to automatically

recover from fault conditions. However, if required,

the user may initialize the device by doing a hardware

or software reset.

Reset Mode

There are two types of reset in the NWK933 - hardware

and software. The hardware reset is activated by

setting the RESET_N pin to logic 0, and holding it low

for at least 100ns. This mode causes an over-all reset

in the NWK933 - both analog and digital circuitry are

reset. Whilst RESET_N is low, the SPDST and FDST

pins are inputs, and are used to determine the speed

and duplex capability which will be advertised during

auto-neg. A low on SPDST advertises 100M capability.

A high on FDST advertises full duplex capability.

The software reset is activated by setting bit 15 in

register 0 high. This bit is a self clear bit and causes

a partial reset of the device.

Figure 5 summarises the different blocks to be reset

and which reset will affect them:

Block

management register

PCS state machine (RCV,

XMT, ANEG)

XMT scrambler

RCV scramble

control state machine

analog

HW Reset

yes

yes

SW reset

yes

yes

yes

yes

yes

yes

yes

No

yes

No

Figure 5. Effects of Reset

Note: Holding RESET_N low will hold the device in a static,

low power state.

5

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