CAT24AC128(2006) Ver la hoja de datos (PDF) - Catalyst Semiconductor => Onsemi
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CAT24AC128
(Rev.:2006)
(Rev.:2006)
Catalyst Semiconductor => Onsemi
CAT24AC128 Datasheet PDF : 11 Pages
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Not Recommended for New Design,
Replace with CAT24C128
A.C. CHARACTERISTICS
VCC = +1.8V to +5.5V, unless otherwise specified
Output Load is 1 TTL Gate and 100pF
Read & Write Cycle Limits
Symbol
Parameter
FSCL
tAA
tBUF(1)
tHD:STA
tLOW
tHIGH
tSU:STA
tHD:DAT
tSU:DAT
tR(1)
tF(1)
tSU:STO
tDH
tWR
tSP
Clock Frequency
SCL Low to SDA Data Out
and ACK Out
Time the Bus Must be Free Before
a New Transmission Can Start
Start Condition Hold Time
Clock Low Period
Clock High Period
Start Condition Setup Time
(for a Repeated Start Condition)
Data In Hold Time
Data In Setup Time
SDA and SCL Rise Time
SDA and SCL Fall Time
Stop Condition Setup Time
Data Out Hold Time
Write Cycle Time
Input Suppression (SDA, SCL)
VCC = 1.8 V - 5.5 V
Min
Max
100
0.1
3.5
4.7
4.0
4.7
4.0
4.0
0
100
1.0
300
4.7
100
5
100
CAT24AC128
VCC = 2.5 V - 5.5 V
Min
Max
400
0.05
0.9
Units
kHz
µs
1.2
µs
0.6
µs
1.2
µs
0.6
µs
0.6
µs
0
ns
100
ns
0.3
µs
300
ns
0.6
µs
50
ns
5
ms
100
ns
Power-Up Timing (1)(2)
Symbol
Parameter
Min Typ Max Units
tPUR
tPUW
Power-Up to Read Operation
Power-Up to Write Operation
1
ms
1
ms
Note:
(1) This parameter is tested initially and after a design or process change that affects the parameter.
(2) tPUR and tPUW are the delays required from the time VCC is stable until the specified operation can be initiated.
The write cycle time is the time from a valid stop condition of a write sequence to the end of the internal program/erase cycle. During
the write cycle, the bus interface circuits are disabled, SDA is allowed to remain high, and the device does not respond to its slave
address.
FUNCTIONAL DESCRIPTION
The CAT24AC128 supports the I2C Bus data
transmission protocol. This Inter-Integrated Circuit Bus
protocol defines any device that sends data to the bus to
be a transmitter and any device receiving data to be a
receiver. The transfer is controlled by the Master device
which generates the serial clock and all START and
STOP conditions for bus access. The CAT24AC128
operates as a Slave device. Both the Master device and
Slave device can operate as either transmitter or receiver,
but the Master device controls which mode is activated.
3
Doc. No. 1028, Rev. J
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