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CAT24AC128

128kbit I2C Serial CMOS EEPROM

Catalyst Semiconductor => Onsemi 

CAT24AC128

to send up to 63 additional bytes. After each byte has

been transmitted, CAT24AC128 will respond with an

acknowledge, and internally increment the six low order

address bits by one. The high order bits remain

unchanged.

If the Master transmits more than 64 bytes before sending

the STOP condition, the address counter ‘wraps around’,

and previously transmitted data will be overwritten.

When all 64 bytes are received, and the STOP condition

has been sent by the Master, the internal programming

cycle begins. At this point, all received data is written to

the CAT24AC128 in a single write cycle.

Acknowledge Polling

Disabling of the inputs can be used to take advantage of

the typical write cycle time. Once the stop condition is

issued to indicate the end of the host's write operation,

CAT24AC128 initiates the internal write cycle. ACK

polling can be initiated immediately. This involves issu-

ing the start condition followed by the slave address for

a write operation. If CAT24AC128 is still busy with the

write operation, no ACK will be returned. If

CAT24AC128 has completed the write operation, an

ACK will be returned and the host can then proceed with

the next read or write operation.

WRITE PROTECTION

The Write Protection feature allows the user to protect

against inadvertent programming of the memory array.

If the WP pin is tied to VCC, the entire memory array is

protected and becomes read only. The CAT24AC128

will accept both slave and byte addresses, but the

memory location accessed is protected from

programming by the device’s failure to send an

acknowledge after the first byte of data is received.

READ OPERATIONS

The READ operation for the CAT24AC128 is initiated in

the same manner as the write operation with one

exception, that R/W bit is set to one. Three different

READ operations are possible: Immediate/Current

Address READ, Selective/Random READ and

Sequential READ.

Immediate/Current Address Read

The CAT24AC128’s address counter contains the

address of the last byte accessed, incremented by one.

In other words, if the last READ or WRITE access was

to address N, the READ immediately following would

access data from address N+1. If N=E (where E=16383),

then the counter will ‘wrap around’ to address 0 and

continue to clock out data. After the CAT24AC128

receives its slave address information (with the R/W bit

set to one), it issues an acknowledge, then transmits the

8 bit byte requested. The master device does not send

an acknowledge, but will generate a STOP condition.

Selective/Random Address Read

Selective/Random READ operations allow the Master

Figure 6. Byte Write Timing

S

T

BUS ACTIVITY: A SLAVE

MASTER R ADDRESS

T

BYTE ADDRESS

A15–A8

A7–A0

S

T

DATA

O

P

SDA LINE S

*=Don't Care Bit

**

A

A

C

C

K

K

P

A

A

C

C

K

K

Figure 7. Page Write Timing

S

T

BUS ACTIVITY: A SLAVE

MASTER R ADDRESS

T

BYTE ADDRESS

A15–A8

A7–A0

DATA

DATA n

S

T

DATA n+63

O

P

SDA LINE S

*=Don't Care Bit

**

P

A

A

A

A

AA

A

C

C

C

C

CC

C

K

K

K

K

KK

K

Doc. No. 1028, Rev. I

6

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