CAT25C08/16
Figure 9. HOLD Timing
CS
SCK
HOLD
tCD
tHD
tHZ
SO
Note: Dashed Line= mode (1, 1) – – – – –
Figure 10. WP Timing
CS
SCK
WP
WP
Note: Dashed Line= mode (1, 1) – – – – –
tCD
tHD
HIGH IMPEDANCE
tLZ
t WPS
t WPH
Doc. No. 1016, Rev. C
10
© 2006 by Catalyst Semiconductor, Inc.
Characteristics subject to change without notice