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CD4047

CMOS Low-Power Monostable/Astable Multivibrator

Intersil 

CD4047BMS

TABLE 9. FUNCTIONAL TERMINAL CONNECTIONS

In all cases External resistor between terminals 2 and 3 (Note 1)

External capacitor between terminals 1 and 3 (Note 1)

FUNCTION

TERMINAL CONNECTIONS

TO VDD

TO VSS

INPUT TO

OUTPUT PULSE

FROM

ASTABLE MULTIVIBRATOR

Free Running

4, 5, 6, 14

7, 8, 9, 12

-

10, 11, 13

True Gating

4, 6, 14

7, 8, 9, 12

5

10, 11, 13

Complement Gating

6, 14

5, 7, 8, 9, 12

4

10, 11, 13

MONOSTABLE MULTIVIBRATOR

Positive Edge Trigger

4, 14

5, 6, 7, 9, 12

8

10, 11

Negative Edge Trigger

4, 8, 14

5, 7, 9, 12

6

10, 11

Retriggerable

4, 14

5, 6, 7, 9

8, 12

10, 11

External Countdown (Note 3)

14

5, 6, 7, 8, 9, 12

-

10, 11

NOTES:

1. See text.

2. First positive 1/2 cycle pulse width = 2.48 RC. See note follow Monostable Mode Design Information.

3. Input Pulse to Reset of External Counting Chip External Counting Chip Output to Terminal 4.

OUTPUT PERIOD OR PULSE

WIDTH

TA (10, 11) = 4.40 RC

TA (13) = 2.20 RC (Note 2)

tM (10, 11) = 2.48 RC

Logic Diagrams

5

ASTABLE

4

ASTABLE

6

-TRIGGER

8 +TRIGGER

RETRIGGER

12

EXTERNAL

9

RESET

C-TIMING

CR

312

R-TIMING

RC

COMMON

ASTABLE

GATE

CONTROL

LOW POWER

ASTABLE

MULTIVIBRATOR

OSCILLATOR OUT

13

FREQUENCY

DIVIDER (÷2)

Q 10

Q

11

MONOSTABLE

CONTROL

RETRIGGER

CONTROL

FIGURE 1. CD4047BMS LOGIC BLOCK DIAGRAM

7-903

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