CDB42406 Ver la hoja de datos (PDF) - Cirrus Logic

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CDB42406

Evaluation Board For CS42406

Cirrus Logic 

CDB42406

1.7.3c Setup 9

Using the on-board crystal oscillator, AUDIO MCLK, a DSP connected to DSP I/O HDR

masters the subclocks for the ADC/DAC and provides data to the DAC. Subclocks for the

ADC are input via DSP_ADC_LRCK and DSP_ADC_SCLK while subclocks for the DAC

are input via DSP_DAC_LRCK and DSP_DAC_SCLK. This allows independent control of

the sample rate for the ADC and DAC. For implementation of this setup option, set DIP

switch S4 (SW[3:0]) to ‘1001’b.

AUDIO

MCLK

CS8416

RMCK

OMCK

OLRCK/

OSCLK

SD OUT

CS8406

OMCK

ILRCK/

ISCLK

SDIN

CS42406

MCLK

DAC_LRCK/

DAC_SCLK

DAC_SDINx

ADC_LRCK/

ADC_SC LK

ADC_SDOUT

DSP I/O

HDR

DSP_M CLK

DS P_DAC_LRCK/

DSP _D AC_SCLK

DS P_SDINx

DS P_ADC_LRCK/

DSP _A DC_SCLK

DSP_SD OU T

Figure 10. DSP Routing - Setup 9

1.7.3d Setup 10

A DSP connected to DSP I/O HDR masters all clocks for the ADC/DAC and provides data

to the DAC. Subclocks for the ADC are input via DSP_ADC_LRCK and DSP_ADC_SCLK

while subclocks for the DAC are input via DSP_DAC_LRCK and DSP_DAC_SCLK. This

allows independent control of the sample rate for the ADC and DAC. For implementation

of this setup option, set DIP switch S4 (SW[3:0]) to ‘1010’b.

A U D IO

MCLK

CS8416

RMCK

OMCK

O LRCK/

OS CLK

SDOUT

CS8406

OMCK

ILR C K /

ISCLK

SDIN

CS42406

MCLK

D A C _L R C K /

D A C _S C L K

D A C _S D IN x

A D C _ L RC K /

A D C _ S C LK

ADC_SDO UT

DSP I/O

HDR

DSP_MCLK

D S P _ D A C _ LR C K /

D S P _ D A C_ S C L K

DS P_SDINx

D S P _ A D C _ LR C K /

D S P _ A D C_ S C L K

DSP_SDOUT

Figure 11. DSP Routing - Setup 10

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